218
Sequence Control Instructions
Section 3-5
Differences between MILH(517) and MILR(518)
Differentiated instructions (DIFU, DIFD, or instructions with a @ or % prefix)
operate differently in interlocks created with MILH(517) and MILR(518).
When a program section is interlocked with MILR(518), a differentiated
instruction will not be executed when the interlock is cleared even if the differ-
entiation condition was activated during the interlock (comparing the status of
the execution condition when the interlock started to its status when the inter-
lock was cleared).
When a program section is interlocked with MILH(517), a differentiated
instruction will be executed when the interlock is cleared if the differentiation
condition was activated during the interlock (comparing the status of the exe-
cution condition when the interlock started to its status when the interlock was
cleared).
MILH
0
MILC
2
MILC
1
MILC
0
MILH
1
MILH
2
Global interlock
(Emergency stop)
Partial interlock
(Conveyor RUN)
A1 (Peripheral processing)
A2 (Conveyor operation)
Partial interlock
(Arm RUN)
A3 (Arm operation)
When the Emergency Stop is ON (input
condition OFF), A1, A2, and A3 are
interlocked.
When the Emergency Stop is OFF (input
condition ON), A1 is executed normally and A2
and A3 are controlled by the Conveyor RUN
and Arm RUN switches as described below.
When the Conveyor RUN switch is OFF (input
condition OFF), both A2 and A3 are interlocked.
When the Conveyor RUN switch is ON (input
condition ON), A2 is executed normally and A3 is
controlled by the Arm RUN switch as described
below.
When the Arm RUN switch is OFF (input
condition OFF), A3 is interlocked.
When the Arm RUN switch is ON (input
condition ON), A3 is executed normally.
Summary of Contents for SYSMAC CS Series
Page 2: ......
Page 4: ...iv ...
Page 30: ...xxx ...
Page 186: ...146 List of Instructions by Function Code Section 2 4 ...
Page 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Page 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Page 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Page 1392: ...1352 ASCII Code Table Appendix A ...
Page 1404: ...1364 Revision History ...