![background image](http://html1.mh-extra.com/html/omron/sysmac-cs-series/sysmac-cs-series_reference-manual_742030211.webp)
171
Sequence Input Instructions
Section 3-3
3-3-6
OR NOT: OR NOT
Purpose
Reverses the status of the specified bit and takes a logical OR with the current
execution condition.
Ladder Symbol
Variations
Note
1.
The following variations are supported by only the CS1-H, CJ1-H, CJ1M,
or CS1D CPU Units: @OR NOT, %OR NOT, !@OR NOT, and !%OR NOT.
2.
Immediate refreshing is not supported by CS1D CPU Units for Duplex-
CPU Systems.
3.
Combined variations are supported by CS1D CPU Units for Single-CPU
Systems and CS1-H, CJ1-H, and CJ1M CPU Units only.
Applicable Program Areas
Operand Specifications
Bus bar
Variations
Creates ON Each Cycle OR NOT Result is ON
OR NOT
Creates ON Once for Upward Differentiation (See
note 1.)
@OR NOT
Creates ON Once for Downward Differentiation (See
note 1.)
%OR NOT
Immediate Refreshing Specification (See note 2.)
!OR NOT
Combined
Variations
Refreshes Input Bit and Creates ON Once for
Upward Differentiation (See note 3.)
!@OR NOT
Refreshes Input Bit and Creates ON Once for
Downward Differentiation (See note 3.)
!%OR NOT
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
OR NOT bit operand
CIO Area
CIO 000000 to CIO 614315
Work Area
W00000 to W51115
Holding Bit Area
H00000 to H51115
Auxiliary Bit Area
A00000 to A95915
Timer Area
T0000 to T4095
Counter Area
C0000 to C4095
Task Flag Area
TK0000 to TK0031
Condition Flags
ER, CY, N, OF, UF, >, =, <, >=, <>, <=, A1, A0
Clock Pulses
0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area
---
DM Area
---
EM Area with bank
---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants
---
Data Registers
---
Summary of Contents for SYSMAC CS Series
Page 2: ......
Page 4: ...iv ...
Page 30: ...xxx ...
Page 186: ...146 List of Instructions by Function Code Section 2 4 ...
Page 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Page 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Page 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Page 1392: ...1352 ASCII Code Table Appendix A ...
Page 1404: ...1364 Revision History ...