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897
High-speed Counter/Pulse Output Instructions
Section 3-21
Variations
Applicable Program Areas
Operands
P: Port Specifier
The port specifier specifies the port where the pulses will be output.
M: Output Mode
The content of M specifies the parameters for the pulse output as follows:
S: First Word of Settings Table
The content of S to S+2 controls the pulse output as shown in the following
diagrams.
Operand Specifications
Variations
Executed Each Cycle for ON Condition
ACC(888)
Executed Once for Upward Differentiation
@ACC(888)
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification
Not supported
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
P
Port
0000 hex
Pulse output 0
0001 hex
Pulse output 1
0
3
4
7
8
11
12
15
M
Mode
0 hex: Continuous mode
1 hex: Independent mode
Direction
0 hex: CW
1 hex: CCW
Pulse output method (See note.)
0 hex: CW/CCW
1 hex: Pulse + direction
Always 0 hex.
Note: Use the same pulse output method when using both pulse outputs 0 and 1.
S+1
S+2
S
0
15
Lower word with target frequency
Upper word with target frequency
0 to 100,000 Hz
(0000 0000 to 0001 86A0 hex)
Specify the frequency after acceleration in Hz.
Acceleration/deceleration rate
1 to 2,000 Hz (0001 to 07D0 hex)
Specify the increase or decrease in the frequency per pulse control period (4 ms).
Area
P
M
S
CIO Area
---
---
CIO 0000 to CIO 6141
Work Area
---
---
W000 to W509
Holding Bit Area
---
---
H000 to H509
Auxiliary Bit Area
---
---
A448 to A957
Timer Area
---
---
T0000 to T4093
Counter Area
---
---
C0000 to C4093
DM Area
---
---
D00000 to D32765
EM Area without bank
---
---
---
EM Area with bank
---
---
---
Summary of Contents for SYSMAC CS Series
Page 2: ......
Page 4: ...iv ...
Page 30: ...xxx ...
Page 186: ...146 List of Instructions by Function Code Section 2 4 ...
Page 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Page 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Page 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Page 1392: ...1352 ASCII Code Table Appendix A ...
Page 1404: ...1364 Revision History ...