![background image](http://html1.mh-extra.com/html/omron/sysmac-cs-series/sysmac-cs-series_reference-manual_742030399.webp)
359
Data Movement Instructions
Section 3-8
Operand Specifications
Description
MOVRW(561) finds the PLC memory address for the PV of the timer or
counter specified in S and writes that address in D (an Index Register).
MOVRW(561) will set the PLC memory address of the timer or counter’s PV in
D. Use MOVR(560) to set the PLC memory address of the timer or counter
Completion Flag.
Flags
Note In CS1-H, CJ1-H, CJ1M, and CS1D (for Single-CPU System) CPU Units,
these Flags are left unchanged.
In CS1 and CJ1 CPU Units, these Flags are turned OFF.
Precautions
MOVRW(561) cannot set the PLC memory addresses of data area words,
bits, or timer/counter Completion Flags. Use MOVR(560) to set these PLC
memory addresses.
Area
S
D
CIO Area
---
Work Area
---
Holding Bit Area
---
Auxiliary Bit Area
---
Timer Area
T0000 to T4095
(present value)
---
Counter Area
C0000 to C4095
(present value)
---
DM Area
---
EM Area without bank
---
EM Area with bank
---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants
---
Data Registers
---
Index Registers
---
IR0 to IR15
Indirect addressing
using Index Registers
---
Internal I/O memory address of S
Timer/counter PV only
Index Register
Name
Label
Operation
Error Flag
ER
Unchanged (See note.)
Equals Flag
=
Unchanged (See note.)
Negative Flag
N
Unchanged (See note.)
Summary of Contents for SYSMAC CS Series
Page 2: ......
Page 4: ...iv ...
Page 30: ...xxx ...
Page 186: ...146 List of Instructions by Function Code Section 2 4 ...
Page 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Page 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Page 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Page 1392: ...1352 ASCII Code Table Appendix A ...
Page 1404: ...1364 Revision History ...