
205
Sequence Output Instructions
Section 3-4
Description
When the execution condition is ON, OUTB(534) turns ON bit N of word D.
When the execution condition is OFF, OUTB(534) turns OFF bit N of word D.
If the immediate refreshing version is not used, the status of the execution
condition (power flow) is written to the specified bit in I/O memory. If the imme-
diate refreshing version is used, the status of the execution condition (power
flow) is written to the Basic Output Unit’s output terminal as well as the output
bit in I/O memory.
OUTB(534) is supported by CS1-H, CJ1-H, and CJ1M CPU Units only.
Flags
There are no flags affected by this instruction.
Precautions
Immediate refreshing (!OUTB(534)) can be specified. An immediate refresh
instruction updates the status of the output terminal just after the instruction is
executed on an output bit allocated to a Basic Output Unit (but not for C200H
Group 2 Multi-point Output Units or Basic Output Units on Slave Racks), at
Timer Area
T0000 to T4095
Counter Area
C0000 to C4095
DM Area
D00000 to D32767
EM Area without bank
E00000 to E32767
EM Area with bank
En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM addresses in
binary
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM addresses in
BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
---
#0000 to #000F (binary)
or &0 to &15
Data Registers
DR0 to DR15
Index Registers
---
Indirect addressing using
Index Registers
,IR0 to ,IR15
–2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to, –(– –) IR15
Area
D
N
15
0
D
N
ON
OFF
ON
OFF
This bit is turned OFF.
Execution condition
Bit N of word D
Summary of Contents for SYSMAC CS Series
Page 2: ......
Page 4: ...iv ...
Page 30: ...xxx ...
Page 186: ...146 List of Instructions by Function Code Section 2 4 ...
Page 1320: ...1280 Model Conversion Instructions Unit Ver 3 0 or Later Section 3 35 ...
Page 1390: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2 ...
Page 1391: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits ...
Page 1392: ...1352 ASCII Code Table Appendix A ...
Page 1404: ...1364 Revision History ...