Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-4
Freescale Semiconductor
to clear security, which involves mass erasing the on-chip flash memory. No other debug access is allowed.
Secure mode can be used in conjunction with each of the wait and stop low-power modes.
If the BDM interface is not enabled, access to the debug resources is limited in the same manner as a secure
device.
If the device is not secure and the BDM interface is enabled (XCSR[ENBDM] is set), the device is
operating in debug mode and additional resources are available via the BDM interface. In this mode, the
status of the processor (running, stopped, or halted) determines which BDM commands may be used.
Debug mode functions are managed through the background debug controller (BDC) in the Version 1
ColdFire core. The BDC provides the means for analyzing MCU operation during software development.
BDM commands can be classified into three types as shown in
.
For more information on these three BDM command classifications, see
The core’s halt mode is entered in a number of ways:
•
The BKGD pin is low during POR
•
The BKGD pin is low immediately after a BDM-initiated force reset (see CSR2[BDFR] in
Section 20.3.3, “Configuration/Status Register 2 (CSR2),”
for details)
•
A background debug force reset occurs (CSR2[BDFR] is set) and CSR2[BFHBR] is set
•
A computer operating properly reset occurs and CSR2[COPHR] is set
•
An illegal operand reset occurs and CSR2[IOPHR] is set
•
An illegal address reset occurs and CSR2[IADHR] is set
•
A BACKGROUND command is received through the BKGD pin. If necessary, this wakes the
device from STOP/WAIT modes.
•
A properly-enabled (XCSR[ENBDM] is set) HALT instruction is executed
•
Encountering a BDM breakpoint and the trigger response is programmed to generate a halt
•
Reaching a PSTB trace buffer full condition when operating in an obtrusive recording mode
(CSR2[PSTBRM] is set to 01 or 11)
Table 20-2. BDM Command Types
Command Type
Flash
Secure?
BDM?
Core Status
Command Set
Always-available
Secure or
Unsecure
Enabled or
Disabled
—
• Read/write access to XCSR[31–24], CSR2[31–24],
CSR3[31–24]
Non-intrusive
Unsecure
Enabled
Run, Halt
• Memory access
• Memory access with status
• Debug register access
• BACKGROUND
Active background
Unsecure
Enabled
Halt
• Read or write CPU registers (also available in stop mode)
• Single-step the application
• Exit halt mode to return to the application program (GO)
