Mini-FlexBus
Freescale Semiconductor
11-16
MCF51CN128 Reference Manual, Rev. 6
Figure 11-13. Single Word-Write Transfer
11.4.6.4
Timing Variations
The Mini-FlexBus module has several features that can change the timing characteristics of a basic read-
or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or
latch data.
11.4.6.4.1
Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCR
n
registers. Wait states
can give the peripheral or memory more time to return read data or sample write data.
FB_CLK
S0
S1
S2
S3
FB_AD[15:0]
FB_R/W
FB_ALE
FB_OE
DATA[15:0]
FB_AD[19:16]
ADDR[19:16]
ADDR[15:0]
Mux’d Bus
FB_CS
n
S0
