Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual,
Rev. 6
8-12
Freescale Semiconductor
8.3.3
INTC Programmable Level 6, Priority {7,6} Registers
(INTC_PL6P{7,6})
The level seven interrupt requests cannot have their levels reassigned. However, any of the remaining
peripheral interrupt requests can be reassigned as the highest priority maskable requests using these two
registers (INTC_PL6P7 and INTC_PL6P6). The vector number associated with the interrupt requests does
not change. Rather, only the interrupt request's level and priority are altered, based on the contents of the
INTC_PL6P{7,6} registers.
Offset: CF1_INT 0x10 (INTC_FRC)
Access: Read/Write
63
62
61
60
59
58
57
56
R
0
LVL1
LVL2
LVL3
LVL4
LVL5
LVL6
LVL7
W
Reset
0
0
0
0
0
0
0
0
Figure 8-3. Force Interrupt Register (INTC_FRC)
Table 8-6. INTC_FRC Field Descriptions
Field
Description
63
Reserved, must be cleared.
62
LVL1
Force Level 1 interrupt.
0 Negates the forced level 1 interrupt request.
1 Forces a level 1 interrupt request.
61
LVL2
Force Level 2 interrupt.
0 Negates the forced level 2 interrupt request.
1 Forces a level 2 interrupt request.
60
LVL3
Force Level 3 interrupt.
0 Negates the forced level 3 interrupt request.
1 Forces a level 3 interrupt request.
59
LVL4
Force Level 4 interrupt.
0 Negates the forced level 4 interrupt request.
1 Forces a level 4 interrupt request.
58
LVL5
Force Level 5 interrupt.
0 Negates the forced level 5 interrupt request.
1 Forces a level 5 interrupt request.
57
LVL6
Force Level 6 interrupt.
0 Negates the forced level 6 interrupt request.
1 Forces a level 6 interrupt request.
55
LVL7
Force Level 7 interrupt.
0 Negates the forced level 7 interrupt request.
1 Forces a level 7 interrupt request.
