Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
6-17
RDIV bits should also be set appropriately here according to the external reference frequency
because although the FLL is bypassed, it remains on in FBE mode.
— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
useful if the application switches back and forth between internal and external modes. For
minimum power consumption, leave the internal reference disabled while in an external clock
mode.
4. After the proper configuration bits have been set, wait for the affected bits in the MCGSC register
to be changed appropriately, reflecting that the MCG has moved into the proper mode.
— If ERCLKEN was set in step 1 or the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and
EREFS was also set in step 1, wait here for the OSCINIT bit to become set indicating that the
external clock source has finished its initialization cycles and stabilized.
— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before
moving on.
— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the
CLKST bits have changed to %10 indicating the external reference clock has been
appropriately selected. Although the FLL is bypassed in FBE mode, it remains on and locks in
FBE mode.
5. Write to the MCGC4 register to determine the DCO output (MCGOUT) frequency range. Make
sure that the resulting bus clock frequency does not exceed the maximum specified bus clock
frequency of the device.
— By default, with DMX32 cleared to 0, the FLL multiplier for the DCO output is 512. For greater
flexibility, if a mid-range FLL multiplier of 1024 is desired instead, set the DRS[1:0] bits to
%01 for a DCO output frequency of 33.55 MHz. If a high-range FLL multiplier of 1536 is
desired instead, set the DRS[1:0] bits to %10 for a DCO output frequency of 50.33 MHz.
— When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %00 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 608 is 19.92 MHz.
— When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %01 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 1216 is 39.85 MHz.
— When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %10 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 1824 is 59.77 MHz.
6. Wait for the LOCK bit in MCGSC to become set, indicating that the FLL has locked to the new
multiplier value designated by the DRS and DMX32 bits.
NOTE
Setting DIV32 (bit 4) in MCGC3 is strongly recommended for FLL external
modes when using a high frequency range (RANGE = 1) external reference
clock. The DIV32 bit is ignored in all other modes.
