Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-47
20.4.1.5.15
READ_CSR2_BYTE
Read the most significant byte of CSR2 (CSR2[31–24]). This command can be executed in any mode.
20.4.1.5.16
READ_CSR3_BYTE
Read the most significant byte of the CSR3 (CSR3[31–24]). This command can be executed in any mode.
20.4.1.5.17
SYNC_PC
Capture the processor’s current PC (program counter) and display it on the PST/DDATA signals. After the
debug module receives the command, it sends a signal to the ColdFire core that the current PC must be
displayed. The core responds by forcing an instruction fetch to the next PC with the address being captured
by the DDATA logic. The DDATA logic captures a 2- or 3-byte instruction address, based on CSR[9]. If
CSR[9] is cleared, then a 2-byte address is captured, else a 3-byte address is captured. The specific
sequence of PST and DDATA values is defined as:
1. Debug signals a SYNC_PC command is pending.
2. CPU completes the current instruction.
3. CPU forces an instruction fetch to the next PC, generating a PST = 0x5 value indicating a taken
branch. DDATA captures the instruction address corresponding to the PC. DDATA generates a PST
marker signalling a 2- or 3-byte address as defined by CSR[9] (CSR[9] = 0, 2-byte; CSR[9] = 1,
3-byte) and displays the captured PC address.
This command can be used to provide a PC synchronization point between the core’s execution and the
application code in the PST trace buffer. It can also be used to dynamically access the PC for performance
Read CSR2 Status Byte
Always Available
0x2E
CSR2
[31–24]
host
→
target
target
→
host
Read CSR3 Status Byte
Always Available
0x2F
CSR3
[31–24]
host
→
target
target
→
host
Synchronize PC to PST/DDATA Signals
Non-intrusive
0x01
host
→
target
D
L
Y
