Pins and Connections
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
2-33
2.4.3
RESET
/PTC3
The RESET/PTC3 pin defaults to hardware reset upon a power-on-reset event. Unless otherwise
programmed, it continues in that role indefinitely. It can also be programmed as an open drain GPIO
output. It should not be programmed as a GPIO input, as an external driver on that pin could drive a zero
on that pin during power up, which would prevent the part from exiting the power-on-reset sequence.
During STOP2, the RESET/PTC3 pin can be used to wake the device from that state. When an application
uses the STOP2 state, RESET/PTC3 must be pre-configured as RESET prior to entering STOP2. There is
a direct analog connection from this pad to the power management controller wakeup pin. PTC3
configured as a GPIO output could prevent proper operation of STOP2.
Using RESET/PTC3 as RESET is optional, since internal power-on reset and low-voltage reset circuitry
typically make external reset circuitry unnecessary. The internal pull-up on this pin is enabled upon any
device reset.
RESET/PTC3 is normally connected to the standard 6-pin background debug connector so a development
system can directly reset the MCU system. If desired, a manual external reset can be added by supplying
a simple switch to ground (pull reset pin low to force a reset).
In EMC-sensitive applications, an external RC filter is recommended on this pin. See
example.
When any reset is initiated (whether from an external source or from an internal source, the
RESET pin is driven low for approximately 66 bus cycles and released. The reset circuity
decodes the cause of reset and records it by setting a corresponding bit in the system control
reset status register (SRS).
2.4.4
IRQ
The IRQ pin function acts as a non-maskable interrupt to the V1 ColdFire core. This function can be
programmed to occur on either PTC4 or PTE5.
2.4.5
Background / Mode Select (BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see bit ENBDM in
“Extended Configuration/Status Register (XCSR),”
for more information), the BKGD/MS pin functions
as a mode select pin. Immediately after any reset, the pin functions as the background pin and can be used
for background debug communication. The internal pull-up on this pin is enabled upon any device reset.
If the BKGD/MS pin is unconnected, the microcontroller enters normal operating mode at the rising edge
of the internal reset after a POR or forced BDC reset. If a debug system is connected to the 6-pin standard
background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a
background debug force reset
1
, which forces the microcontroller into halt mode.
The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a
custom protocol that uses 16 clock cycles of the target microcontroller’s BDC clock per bit time. The target
1. Specifically, BKGD must be held low through the first 16 cycles after deassertion of the internal reset.
