Serial Communication Interface (SCI)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
13-8
13.2.3
SCI Control Register 2 (SCIxC2)
This register can be read or written at any time.
1
PE
Parity Enable. Enables hardware parity generation and checking. When parity is enabled, the most significant bit
(msb) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type. Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
Figure 13-7. SCI Control Register 2 (SCIxC2)
Table 13-4. SCIxC2 Field Descriptions
Field
Description
7
TIE
Transmit Interrupt Enable (for TDRE)
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
6
TCIE
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupts from TC disabled (use polling).
1 Hardware interrupt requested when TC flag is 1.
5
RIE
Receiver Interrupt Enable (for RDRF)
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4
ILIE
Idle Line Interrupt Enable (for IDLE)
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.
Table 13-3. SCIxC1 Field Descriptions (continued)
Field
Description
