NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Mini-FlexBus
11-7 Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
11.4 Functional Description
11.4.1 Chip-Select Operation
Each chip-select has a dedicated set of registers for configuration and control:
• Chip-select address registers (CSAR n ) control the base address space of the chip-select. See
Section 11.3.1, “Chip-Select Address Registers (CSAR0 – CSAR1).”
• Chip-select mask registers (CSMR n ) provide 16-bit address masking and access control. See
Section 11.3.2, “Chip-Select Mask Registers (CSMR0 – CSMR1).”
• Chip-select control registers (CSCR n ) provide port size, wait-state generation, address setup and
hold times, and automatic acknowledge generation features. See Section 11.3.3, “Chip-Select
Control Registers (CSCR0 – CSCR1).”
11.4.1.1 General Chip-Select Operation
When a bus cycle is routed to the Mini-FlexBus, the device first compares its address with the base address
and mask configurations programmed for chip-selects 0 and 1 (configured in CSCR0 – CSCR1). The
results depend on if the address matches or not as shown in
Table 11-6 .
11.4.1.2 8- and 16-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. The processor always drives a
20-bit address on the FB_AD bus regardless of the external device’s address size. The external device must
7–6
PS
Port size. Specifies the data port width associated with each chip-select. It determines where data is driven during
write cycles and where data is sampled during read cycles.
00 Reserved
01 8-bit port size. Valid data sampled and driven on FB_D[7:0]
1
x 16-bit port size. Valid data sampled and driven on FB_AD[15:0]. Only supported in multiplexed mode.
5–0 Reserved, must be cleared.
Table 11-6. Results of Address Comparison
Address Matches
CSAR n ?
Result
Yes,
one CSAR
The appropriate chip-select is asserted, generating an external bus cycle as defined in the chip-select
control register.
If CSMR[WP] is set and a write access is performed, the internal bus cycle terminates with a bus error,
no chip select is asserted, and no external bus cycle is performed.
No The internal bus cycle terminates with a bus error, no chip select is asserted, and no external bus cycle
is performed.
Yes,
multiple CSARs
The internal bus cycle terminates with a bus error, no chip select is asserted, and no external bus cycle
is performed.
Table 11-5. CSCR n Field Descriptions (continued)
Field Description