Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
17-29
Figure 17-11. Typical IIC Interrupt Routine
Master
Mode
?
Tx/Rx
?
Last Byte
Transmitted
?
RXAK=0
?
End of
Addr Cycle
(Master Rx)
?
Write Next
Byte to IICD
Switch to
Rx Mode
Dummy Read
from IICD
Generate
Stop Signal
Read Data
from IICD
and Store
Set TXACK =1
Generate
Stop Signal
2nd Last
Byte to Be Read
?
Last
Byte to Be Read
?
Arbitration
Lost
?
Clear ARBL
IAAS=1
?
IAAS=1
?
SRW=1
?
TX/RX
?
Set TX
Mode
Write Data
to IICD
Set RX
Mode
Dummy Read
from IICD
ACK from
Receiver
?
Tx Next
Byte
Read Data
from IICD
and Store
Switch to
Rx Mode
Dummy Read
from IICD
RTI
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
Y
TX
RX
RX
TX
(Write)
(Read)
N
Address Transfer
(MST = 0)
(MST = 0)
See Note 1
Y
N
FACK?
Flow Chart1
See Note 2
Clear IICIF
Set Fack = 0
Set TXAK
To proper
Value
Clear IICIF
Clear IICIF
Set TXAK to
Proper Value
Clear IICIF
SLTF?
N
Y
Clear IICIF
See Note 3
NOTES:
1. If general call siicaen is enabled, a check must be done to determine whether the received address was a general call address (0x00) or SMbus device default
address. If the received address was one of them, then it must be handled by user software.
2. Flow chart1 means
Typical IIC Interrupt Routine.
3. Delay about 1-2bit scl cycle waiting data register updated then clear IICIF
