Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-32
Freescale Semiconductor
MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The
host should sample the bit level about 10 cycles after it started the bit time.
Figure 20-17. BDC Target-to-Host Serial Bit Timing (Logic 1)
shows the host receiving a logic 0 from the target MCU. Because the host is asynchronous
to the target MCU, there is a 0–1 cycle delay from the host-generated falling edge on BKGD to the start
of the bit time as perceived by the target MCU. The host initiates the bit time, but the target MCU finishes
it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock
cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles
after starting the bit time.
HOST SAMPLES BKGD PIN
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
BKGD PIN
R-C RISE
10 CYCLES
EARLIEST START
OF NEXT BIT
