Modes of Operation
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
3-7
3.6
Run Modes
3.6.1
Run Mode
Run mode is the normal operating mode for this device. This mode is selected when the BKGD/MS pin is
high at the rising edge of the internal reset signal. Upon exiting reset, the CPU fetches the supervisor SR
and initial PC from locations 0x(00)00_0000 and 0x(00)00_0004 and executes code starting at the newly
set value of the PC.
3.6.2
Low-Power Run Mode (LPrun
1
)
In the low-power run mode, the on-chip voltage regulator is put into its standby (or loose regulation) state.
In this state, the power consumption is reduced to a minimum that allows CPU functionality. To further
reduce power consumption, disable the clocks to all unused peripherals by clearing the corresponding bits
in SCGC1 - 4 registers
2
.
Before entering this mode, the following conditions must be met:
•
BLPE
3
is the selected clock mode for the MCG. See
Section 6.4.1, “MCG Modes of Operation,”
for more details.
•
The bus frequency is less than 125 kHz.
•
The ADC is in low-power mode (ADCCFG[ADLPC]=1) or disabled.
•
Low-voltage detect is disabled. The LVDE and/or LVDSE bit in SPMSC1 register is cleared.
•
Flash programming/erasing is not allowed
After these conditions are met, low-power run mode can be entered by setting SPMSC2[LPR].
To re-enter standard run mode, clear the LPR bit. SPMSC2[LPRS] is a read-only status bit that can be used
to determine if the regulator is in full-regulation mode or not. When LPRS is cleared, the regulator is in
full-regulation mode and the MCU can run at full speed in any clock mode.
Low-power run mode can return to full regulation if any interrupt occurs by setting SPMSC2[LPWUI].
The MCG FLLs can then be set for full speed immediately in the interrupt service routine.
3.6.2.1
BDM in Low-Power Run Mode
Low-power run mode cannot be entered when the MCU is in active background debug mode.
1. If a device is in low power run mode, a falling edge on an active BKGD/MS pin exits low power run mode, clears the LPRS bits
and returns the device to normal run mode.
2. System clock gating control registers 1, 2, 3 and 4
3. FLL bypassed external low-power
