NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

Page: 126 / 487

Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-14 Freescale Semiconductor
5.7.3 System Options 1 Register (SOPT1)
This register has three write-once bits and one write anytime bit. For the write-once bits, only the first write
after reset is honored. All bits in the register can be read at any time. Any subsequent attempt to write a
write-once bit is ignored to avoid accidental changes to these sensitive settings. SOPT1 must be written
during the reset initialization program to set the desired controls, even if the desired settings are the same
as the reset settings.
2
LOC
Loss-of-Clock Reset — Reset was caused by a loss of external clock. MCGC3[CME] must be set for this func-
tion to operate.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
LVD
Low Voltage Detect — If the LVD is enabled with LVDRE set, and the supply drops below the LVD trip voltage,
an LVD reset occurs. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
7 6 5 4 3 2 1 0
R 0
SL STOPE
1
WAITE COPT
1
COPCLKS
1
COPW
1
W
Reset: 0 0 0 1 1 1 0 0
1
These bits can be written only one time after reset. Subsequent writes are ignored.
Figure 5-3. System Options 1 Register (SOPT1)
Table 5-6. SOPT1 Field Descriptions
Field Description
7 Reserved, must be cleared.
6
SL
Security Level — If security is enabled by the mechanisms outlined in Section 4.5, “Security ”, then this bit affects
what CPU operations can access off-chip by the Mini-FlexBus interface. This bit has no effect if security is not
enabled.
0 All off-chip accesses (opcode and data) by the Mini-FlexBus are disallowed.
1 Off-chip opcode accesses are disallowed. Data accesses are allowed.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop and wait modes are disabled and
a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending on
CPUCR[IRD].
4
WAITE
WAIT Mode Enable — This write-anytime bit is used to enable wait mode. If stop and wait modes are disabled
and a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending
on CPUCR[IRD].
3–2
COPT
COP Watchdog Time-out — These write-once bits select the time-out period of the COP. COPT along with
SOPT2[COPCLKS] defines the COP time-out period as described in Table 5-7 .
Table 5-5. SRS Register Field Descriptions (continued)
Field Description