Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-59
Another example of a variant branch instruction is a JMP (A0) instruction.
entries that indicate a JMP (A0) execution, assuming CSR[BTB] was programmed to display the lower
two bytes of an address.
The PST of 0x05 indicates a taken branch and the marker value 0x0D indicates a 2-byte address.
Therefore, the following entries display the lower two bytes of address register A0, right-shifted by 1, in
least-to-most-significant nibble order. The next PST entry after the JMP instruction completes depends on
the target instruction. See
Section 20.4.3.2, “PST Trace Buffer (PSTB) Entry Format,”
for entry
descriptions explaining the 2-bit prefix before each address nibble.
20.4.3.2
PST Trace Buffer (PSTB) Entry Format
As PST and DDATA values are captured and loaded in the trace buffer, each entry is six bits in size
therefore, the type of the entry can easily be determined when post-processing the PSTB. See
.
Figure 20-25. V1 PST/DDATA Trace Buffer Entry Format
20.4.3.3
PST/DDATA Example
In this section, an example showing the behavior of the PST/DDATA functionality is detailed. Consider
the following interrupt service routine that counts the interrupt, negates the IRQ, performs a software
IACK, and then exits. This example is presented here because it exercises a considerable set of the
PST/DDATA capabilities.
_isr:
PST/DDATA Values
Description
0x05
Taken Branch
0x0D
2-byte Address Marker
{10, Address[4:1]}
Address >> 1
{10, Address[8:5]}
{10, Address[12:9]}
{10, Address[16:13]}
Figure 20-24. Example JMP Instruction Output in PSTB
5
4
3
2
1
0
PSTB[PST]
0
PST[4:0]
Data
PSTB[DDATA]
1
R/W
Data[3:0]
Address
PSTB[DDATA]
1
0
Address[3:0]
1
1
Depending on which nibble is displayed (as determined by CSR[9:8]), Address[3:0] sequentially
(least-to-most-significant nibble order) displays four bits of the real CPU address [16:1] or [24:1].
Reset:
—
—
—
—
—
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