Fast Ethernet Controller (FEC)
16-26
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
NOTE
After the software driver has set up the buffers for a frame, it should set up
the corresponding BDs. The last step in setting up the BDs for a transmit
frame is setting the R bit in the first BD for the frame. The driver must
follow that with a write to TDAR that triggers the FEC to poll the next BD
in the ring.
Table 16-27. Transmit Buffer Descriptor Field Definitions
Word
Field
Description
0
15
R
Ready. Written by the FEC and you.
0 The data buffer associated with this BD is not ready for transmission. You are free to manipulate
this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted
or after an error condition is encountered.
1 The data buffer, prepared for transmission by you, has not been transmitted or currently transmits.
You may write no fields of this BD after this bit is set.
0
14
TO1
Transmit software ownership. This field is reserved for software use. This read/write bit is not modified
by hardware nor does its value affect hardware.
0
13
W
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.
0
12
TO2
Transmit software ownership. This field is reserved for use by software. This read/write bit is not
modified by hardware nor does its value affect hardware.
0
11
L
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame
1 The buffer is the last in the transmit frame
0
10
TC
Transmit CRC. Written by user (only valid if L is set).
0 End transmission immediately after the last data byte
1 Transmit the CRC sequence after the last data byte
0
9
ABC
Append bad CRC. Written by user (only valid if L is set).
0 No effect
1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value)
0
8–0
Reserved, must be cleared.
2
15–0
Data
Length
Data length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never
modified by the FEC.
4
15–0
A[31:16]
Tx data buffer pointer, bits [31:16]
1
1
The transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. The
buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
6
15–0
A[15:0]
Tx data buffer pointer, bits [15:0]
