NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 17-5
17.3.3 IIC Frequency Divider Register (IICF)
For example, if the bus speed is 8 MHz, the table below shows the possible hold time values with different
ICR and MULT selections to achieve an IIC baud rate of 100 kbps
Table 17-2. IICA1 Field Descriptions
Field Description
7:1
AD[7:1]
Slave Address 1 — The AD[7:1] field contains the slave address for the IIC module. This field is used on the 7-bit
address scheme and the lower seven bits of the 10-bit address scheme.
7 6 5 4 3 2 1 0
R
MULT ICR
W
Reset 0 0 0 0 0 0 0 0
Figure 17-3. IIC Frequency Divider Register (IICF)
Table 17-3. IICF Field Descriptions
Field Description
7:6
MULT
IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
5:0
ICR
IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
bits are used to determine the IIC baud rate, the SDA hold time, the SCL Start hold time and the SCL Stop hold
time.
Table 17-4 provides the SCL divider and hold values for corresponding values of the ICR.
The SCL divider multiplied by multiplier factor mul is used to generate IIC baud rate.
IIC baud rate = bus speed (Hz)/(mul * SCL divider) Eqn. 17-1
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
SDA hold time = bus period (s) * mul * SDA hold value Eqn. 17-2
SCL Start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
falling edge of SCL (IIC clock).
SCL Start hold time = bus period (s) * mul * SCL Start hold value Eqn. 17-3
SCL Stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA (IIC data) while SCL is high (Stop condition).
SCL Stop hold time = bus period (s) * mul * SCL Stop hold value Eqn. 17-4