Fast Ethernet Controller (FEC)
Freescale Semiconductor
16-17
MCF51CN128 Reference Manual, Rev. 6
16.4.14 Descriptor Individual Lower Address Register (IALR)
IALR contains the lower 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the DA field of receive frames with an individual
DA. This register is not reset and you must initialize it.
16.4.15 Descriptor Group Upper Address Register (GAUR)
GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a multicast address. You must initialize this register.
Offset: 0x118
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
IADDR1
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 16-14. Descriptor Individual Upper Address Register (IAUR)
Table 16-16. IAUR Field Descriptions
Field
Description
31–0
IADDR1
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast
address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
Offset: 0x11C
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
IADDR2
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 16-15. Descriptor Individual Lower Address Register (IALR)
Table 16-17. IALR Field Descriptions
Field
Description
31–0
IADDR2
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast
address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
Offset: 0x120
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
GADDR1
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 16-16. Descriptor Group Upper Address Register (GAUR)
