Fast Ethernet Controller (FEC)
16-20
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
16.4.20 Receive Descriptor Ring Start Register (ERDSR)
ERDSR points to the start of the circular receive buffer descriptor queue in external memory. This pointer
must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16).
This register is not reset and must be initialized prior to operation.
16.4.21 Transmit Buffer Descriptor Ring Start Registers (ETSDR)
ETSDR provides a pointer to the start of the circular transmit buffer descriptor queue in external memory.
This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly
divisible by 16). You should write zeros to bits 1 and 0. Hardware ignores non-zero values in these two bit
positions.
This register is undefined at reset and must be initialized prior to operation.
Table 16-22. FRSR Field Descriptions
Field
Description
31–11
Reserved, must be cleared.
10
Reserved, must be set.
9–2
R_FSTART
Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper
operation, ensure that R_FSTART is set to 0x48 or greater.
1–0
Reserved, must be cleared.
Offset: 0x180
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
R_DES_START
0
0
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 16-21. Ethernet Receive Descriptor Ring Start Register (ERDSR)
Table 16-23. ERDSR Field Descriptions
Field
Description
31–2
R_DES_START
Pointer to start of receive buffer descriptor queue.
1–0
Reserved, must be cleared.
Offset: 0x184
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
X_DES_START
0
0
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 16-22. Transmit Buffer Descriptor Ring Start Register (ETDSR)
