NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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ColdFire Core
7-12 Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. In addition, the ISA_C architecture includes an instruction (STLDSR) that
stores the current interrupt mask level and loads a value into the SR. This instruction is specifically
intended for use as the first instruction of an interrupt service routine that services multiple interrupt
requests with different interrupt levels. Finally, the V1 ColdFire core includes the CPUCR[IME] bit that
forces the processor to automatically raise the mask level to 7 during the interrupt exception, removing the
need for any explicit instruction in the service routine to perform this function. For more details, see
ColdFire Family Programmer’s Reference Manual .
7.3.2.1 Exception Stack Frame Definition
Figure 7-10 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)
and the 16-bit status register, and the second longword contains the 32-bit program counter address.
2 0x008 Fault Access error
3 0x00C Fault Address error
4 0x010 Fault Illegal instruction
5–7 0x014–0x01C — Reserved
8 0x020 Fault Privilege violation
9 0x024 Next Trace
10 0x028 Fault Unimplemented line-A opcode
11 0x02C Fault Unimplemented line-F opcode
12 0x030 Next Debug interrupt
13 0x034 — Reserved
14 0x038 Fault Format error
15–23 0x03C–0x05C — Reserved
24 0x060 Next Spurious interrupt
25–31 0x064–0x07C — Reserved
32–47 0x080–0x0BC Next Trap # 0-15 instructions
48–60 0x0C0–0x0F0 — Reserved
61 0x0F4 Fault Unsupported instruction
62–63 0x0F8–0x0FC — Reserved
64–102 0x100–0x198 Next Device-specific interrupts
103–255 0x19C–0x3FC — Reserved
1
Fault refers to the PC of the instruction that caused the exception. Next refers to the PC
of the instruction that follows the instruction that caused the fault.
Table 7-6. Exception Vector Assignments (continued)
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment