Parallel Input/Output Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
9-6
9.2.2.2
Port x Slew Rate Enable Register (PTxSE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PT
x
SE[n]). When enabled, slew control limits the rate at which an output can transition in order
to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
9.2.2.3
Port x Drive Strength Selection Register (PTxDS)
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PT
x
DS[n]). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, ensure that the total
current source and sink limits for the MCU are not exceeded. Drive strength selection is intended to affect
the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive
a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of
this, the EMC emissions may be affected by enabling pins as high drive.
7
6
5
4
3
2
1
0
R
PTxSE7
PTxSE6
PTxSE5
PTxSE4
PTxSE3
PTxSE2
PTxSE1
PTxSE0
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-3. Slew Rate Enable for Port x Register (PTxSE)
Table 9-8. PTxSE Field Descriptions
Field
Description
7–0
PTxSE
n
Output Slew Rate Enable for Port x Bits
— Each of these control bits determines if the output slew rate control
is enabled for the associated PTx pin. For Port x pins configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port x bit
n
.
1 Output slew rate control enabled for Port x bit
n
.
7
6
5
4
3
2
1
0
R
PTxDS7
PTxDS6
1
1
The PTD[6](BKGD/MS) pin's drive strength can not be changed by this register and is always high.
PTxDS5
PTxDS4
PTxDS3
PTxDS2
PTxDS1
PTxDS0
W
Reset:
0
1
0
0
0
0
0
0
Figure 9-4. Drive Strength Selection for Port x Register (PTxDS)
Table 9-9. PTxDS Field Descriptions
Field
Description
7–0
PTxDS
n
Output Drive Strength Selection for Port x Bits
— Each of these control bits selects between low and high
output drive for the associated PTx pin. For Port x pins configured as inputs, these bits have no effect.
0 Low output drive strength selected for Port x bit
n
.
1 High output drive strength selected for Port x bit
n
.
