NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Device Overview
MCF51CN128 Reference Manual
,
Rev. 6
1-8 Freescale Semiconductor
1.4 System Clock Generation and Distribution
1.4.1 Clock Distribution Diagram
Figure 1-3 shows how clocks from the MCG and XOSC are distributed to the microcontroller’s other
functional units. Some modules in the microcontroller have selectable clock inputs. All memory-mapped
registers associated with the modules (except RGPIO) are clocked with BUSCLK. The RGPIO registers
are clocked with the CPU clock (MCGOUT).
Figure 1-3. Clock Distribution Diagram
The TPMx and MTIMx external clocks can be assigned to TMRCLK1 or TMRCLK2. See Section 5.7.14,
“SIM Internal Peripheral Select Register (SIMIPS) ”, for details
MCG
Notes
1
The ADC has minimum and maximum frequency requirements. See the Chapter 15, “Analog-to-Digital Converter
(ADC12) ” and the MCF51CN128 Data Sheet .
2
Flash memory has frequency requirements for program and erase operations. See the MCF51CN128 Data Sheet .
3
IICx module uses the full speed core clock for input filtering only.
4
* The fixed frequency clock (FFCLK) is internally synchronized to the bus clock (BUSCLK) and must not exceed one
half of the bus clock frequency.
XT
AL
XOSC
EXT
AL
RTC COP
MTIM1 KBI &
TMRCLK1 &
TPM1
CPU
DBG
RGPIO
TPM2
SCI1
SCI2
SPI1
SPI2
RAM BDM
FEC
ADC FLASH
IIC1
IIC2
MCGIRCLK
MCGERCLK
LPOCLK
MCGFFCLK
MCGOUT
MCGLCLK
1 kHz LPO
÷
2
÷
2
SYNC*
FFCLK*
BUSCLK
OSCOUT
TMRCLK2
MTIM2
SCI3
GPIO
PHYCLK
PMC
wakeup from STOP2
Interrupt
Controller
Mini-
FlexBus