Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
5-10
Freescale Semiconductor
5.5
Low-Voltage Detect (LVD) System
The MCF51CN128 series microcontroller includes a system to protect against low voltage conditions to
protect memory contents and control microcontroller system states during supply voltage variations. The
system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip
voltage, high (V
LVDH
) or low (V
LVDL
). The LVD circuit is enabled when the SPMSC1[LVDE] bit is set
and the trip voltage is selected by the SPMSC3[LVDV] bit. If LVDE and LVDSE are set when the STOP
instruction is processed, the device enters STOP4 mode. The LVD can be left enabled in this mode.
5.5.1
Power-On Reset Operation
When power is initially applied to the microcontroller, or when the supply voltage drops below the
power-on reset re-arm voltage level, V
POR
, the POR circuit causes a reset condition. As the supply voltage
rises, the LVD circuit holds the microcontroller in reset until the supply has risen above the LVD low
threshold, V
LVDL
. Both the POR bit and the LVD bit in SRS are set following a POR.
5.5.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system holds the microcontroller in reset until the supply voltage has risen above the
low voltage detection threshold. The SRS[LVD] bit is set following an LVD reset or POR.
5.5.3
LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then SPMSC1[LVDF] is set and an LVD interrupt
request occurs. The LVDF bit is cleared by writing a 1 to SPMSC1[LVDACK].
5.5.4
Low-Voltage Warning (LVW) Interrupt Operation
The LVD system has a low voltage warning flag (LVWF) to indicate that the supply voltage is
approaching, but is above, the LVD voltage. The LVW also has an interrupt associated with it, enabled by
setting the SPMSC3[LVWIE] bit. If enabled, an LVW interrupt request occurs when the LVWF is set.
LVWF is cleared by writing a 1 to the SPMSC3[LVWACK] bit. There are two user-selectable trip voltages
for the LVW, one high (V
LVWH
) and one low (V
LVWL
). The trip voltage is selected by SPMSC3[LVWV]
bit.
1
Exception vector numbers not appearing in this table are not applicable to the V1 core and
are reserved.
2
The execution of the ILLEGAL instruction (0x4AFC) always generates an illegal instruction
exception, regardless of the state of CPUCR[30].
