Mini-FlexBus
Freescale Semiconductor
11-6
MCF51CN128 Reference Manual, Rev. 6
Table 11-5. CSCR
n
Field Descriptions
Field
Description
31–22
Reserved, must be cleared
21–20
ASET
Address setup. This field controls the assertion of the chip-select with respect to assertion of a valid address and
attributes. The address and attributes are considered valid at the same time FB_ALE asserts.
00 Assert FB_CS
n
on first rising clock edge after address is asserted. (Default FB_CS1)
01 Assert FB_CS
n
on second rising clock edge after address is asserted.
10 Assert FB_CS
n
on third rising clock edge after address is asserted.
11 Assert FB_CS
n
on fourth rising clock edge after address is asserted. (Default FB_CS0)
19–18
RDAH
Read address hold or deselect. This field controls the address and attribute hold time after the termination during a
read cycle that hits in the chip-select address space.
Note:
The hold time applies only at the end of a transfer. Therefore, during a transfer to a port size smaller than the
transfer size, the hold time is only added after the last bus cycle.
The number of cycles the address and attributes are held after FB_CS
n
negation depends on the value of
CSCR
n
[AA] as shown below.
17–16
WRAH
Write address hold or deselect. This field controls the address, data, and attribute hold time after the termination of
a write cycle that hits in the chip-select address space.
Note:
The hold time applies only at the end of a transfer. Therefore, during a transfer to a port size smaller than the
transfer size, the hold time is only added after the last bus cycle.
00 Hold address and attributes one cycle after FB_CS
n
negates on writes. (Default FB_CS1)
01 Hold address and attributes two cycles after FB_CS
n
negates on writes.
10 Hold address and attributes three cycles after FB_CS
n
negates on writes.
11 Hold address and attributes four cycles after FB_CS
n
negates on writes. (Default FB_CS0)
15–10
WS
Wait states. The number of wait states inserted after FB_CS
n
asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states).
9
MUX
Multiplexed mode. Selects between multiplexed and non-multiplexed address/data bus.
0 Non-multiplexed configuration. Address information is driven on FB_ADn and data is read/written on FB_dn.
1 Non-multiplexed configuration. Address information is driven on FB_ADn, and low-order address lines
(FB_AD[7:0] for byte port size or FB_AD[15:0] for word port size) must be latched using the falling edge of FB_ALE
as the latch enable. Data is read/written on FB_AD[7:0] for byte port size and FB_AD[15:0] for word port size.
8
AA
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by
the chip-select address. This bit must be set.
0 Reserved
1 Internal transfer acknowledge is asserted as specified by WS
Note:
This bit must be set, since only internal termination is supported by the Mini-FlexBus.
RDAH
AA = 1
00
(FB_CS1 Default)
0 cycles
01
1 cycles
10
2 cycles
11
(FB_CS0 Default)
3 cycles
