Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
8-11
8.3.2
Force Interrupt Register (INTC_FRC)
The INTC_FRC register allows software to generate a unique interrupt for each possible level at the lowest
priority within the level for functional or debug purposes. These interrupts may be self-scheduled by
setting one or more of the bits in the INTC_FRC register. In some cases, the handling of a normal interrupt
request may cause critical processing by the service routine along with the scheduling (using the
INTC_FRC register) of a lower priority level interrupt request to be processed at a later time for
less-critical task handling.
The INTC_FRC register may be modified directly using a read-modify-write sequence or through a simple
write operation using the set/clear force interrupt registers (INTC_SFRC, INTC_CFRC).
NOTE
Take special notice of the bit numbers within this register, 63–56. This is for
compatibility with other ColdFire interrupt controllers.
Offset: CF1_INT 0x0C (INTC_ORMR)
Access: Read/Write
15
14
13
12
11
10
9
8
R
0
0
0
0
0
0
0
FECDO
W
Reset
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
R
0
0
SCI3DO
0
0
0
0
0
W
Reset
0
0
1
0
0
0
0
0
Figure 8-2. Interrupt OR Mask Register (INTC_ORMR)
Table 8-5. INTC_ORMR Register Descriptions
Field
Description
15-9
Reserved, must be cleared.
8
FECDO
Disable (mask) FEC_Other interrupt request
0 FEC_Other interrupt request is enabled; all individual FEC interrupt requests except FEC_TXF and FEC_RXF are
disabled
1 FEC_Other interrupt request is disabled; all individual FEC interrupt requests are enabled
7–6
Reserved, must be cleared.
5
SCI3DO
Disable (mask) SCI3_OR interrupt request
0 SCI3_OR request is enabled; all individual SCI3 interrupt requests SCI3_{err, tx, rx} are disabled
1 SCI3_OR request is disabled; all individual SCI3 interrupt requests SCI3_{err, tx, rx} are enabled
4-0
Reserved, must be cleared.
