NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Memory
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 4-25
• Fast program and sector erase operation
• Burst program command for faster flash array program times
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection (on any 2 KB memory boundary)
• Security feature to prevent unauthorized access to on-chip memory and resources
• Auto power-down for low-frequency read accesses
4.4.2 Register Descriptions
The flash controller (FTSR) contains a set of 16 control and status registers as shown in Table 4-7 . Detailed
descriptions of each register bit are provided in the following sections.
4.4.2.1 Flash Clock Divider Register (FCDIV)
The FCDIV register controls the length of timed events in program and erase algorithms executed by the
flash memory controller. All bits in the FCDIV register are readable and writable with restrictions as
determined by the value of FDIVLD when writing to the FCDIV register.
Table 4-7. FTSR Register Memory Map and Bit Locations
Address Register Bit 7 6 5 4 3 2 1 Bit 0
0x(FF)FF_82E0 FCDIV FDIVLD PRDIV8 FDIV
0x(FF)FF_82E1 FOPT KEYEN 0 0 0 0 SEC
0x(FF)FF_82E2 RESERVED
FRSV0
— — — — — — — —
0x(FF)FF_82E3 FCNFG CBEIE CCIE KEYACC 0 0 0 0 0
0x(FF)FF_82E4 FPROT FPS FPOPE
N
0x(FF)FF_82E5 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
0x(FF)FF_82E6 FCMD 0 FCMD
0x(FF)FF_82E7
-
0x(FF)FF_82EF
RESERVED — — — — — — — —
7 6 5 4 3 2 1 0
R
FDIVLD PRDIV8 FDIV
W
Reset 0 0 0 0 0 0 0 0
Figure 4-4. Flash Clock Divider Register (FCDIV)