Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
17-9
17.3.5
IIC Status Register (IICS)
7
6
5
4
3
2
1
0
R
TCF
IAAS
BUSY
ARBL
0
SRW
IICIF
RXAK
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-5. IIC Status Register (IICS)
Table 17-6. IICS Field Descriptions
Field
Description
7
TCF
Transfer Complete Flag
— This bit is set on the completion of a byte and acknowledge bit transfer. Note that
this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF
bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode.
0 Transfer in progress.
1 Transfer complete.
6
IAAS
Addressed as a Slave
— The IAAS bit is set when one of the following conditions is met
1) When the calling address matches the programmed slave address,
2) If the GCAEN bit is set and a general call is received.
3) If SIICAEN bit is set, when the calling address matches the second programmed slave address
4) If ALERTEN bit is set and SMBus alert response address is received
This bit is set before ACK bit. The CPU needs to check the SRW bit and set TX/RX bit accordingly. Writing the
IICC1 register with any value clears this bit.
0 Not addressed.
1 Addressed as a slave.
5
BUSY
Bus Busy
— The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is
set when a START signal is detected and cleared when a STOP signal is detected.
0 Bus is idle.
1 Bus is busy.
4
ARBL
Arbitration Lost
— This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be
cleared by software, by writing a 1 to it.
0 Standard bus operation.
1 Loss of arbitration.
2
SRW
Slave Read/Write
— When addressed as a slave the SRW bit indicates the value of the R/W command bit of
the calling address sent to the master.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
