Parallel Input/Output Control
MCF51CN128 Reference Manual, Rev. 6
9-9
Freescale Semiconductor
9.3.2.1
Port x Data Register (PTxD)
The data register of each port allows software to interact with the pins of the chip. Each bit of each data
register controls one pin on the chip. When the port bit is configured as an input (PTxDD[n]=0), a read of
the port returns the logic value of the external pin input for that bit location. When the port bit is configured
as an output (PTxDD[n]=1), a read of the port returns the state of the internal data register bit.
Writing to the data register changes the values of all internal data register bits to the value being written
regardless of the associated DD bit.
9.3.2.2
Port x Data Direction Register (PTxDD)
The PTxDD registers control the direction of the port x pins.
7
6
5
4
3
2
1
0
R
PTxD7
PTxD6
PTxD5
PTxD4
PTxD3
PTxD2
PTxD1
PTxD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-7. Port x Data Register (PTxD)
Table 9-12. PTxD Field Descriptions
Field
Description
7–0
PTxD
n
Port x Data Register Bits
— For Port x pins that are inputs, reads return the logic level on the pin. For Port x
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For Port x pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTxD to all zeroes. Since reset configures all port pins as high-impedence inputs, these zeroes are
not driven onto the pins.
7
6
5
4
3
2
1
0
R
PTxDD7
PTxDD6
PTxDD5
PTxDD4
PTxDD3
PTxDD2
PTxDD1
PTxDD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-8. Port x Data Direction Register (PTxDD)
Table 9-13. PTxDD Field Descriptions
Field
Description
7–0
PTxDD
n
Data Direction for Port x Bits
— These read/write bits control the direction of Port x pins and what is read for
PTxD reads.
0 Input (output driver disabled) and PTxD reads return the pin value.
1 Output driver enabled for Port x bit
n
and PTxD reads return the contents of PTxD
n
.
