Mini-FlexBus
Freescale Semiconductor
11-2
MCF51CN128 Reference Manual, Rev. 6
11.1.2
Features
Key Mini-FlexBus features include:
•
Two independent, user-programmable chip-select signals (FB_CS[1:0]) that can interface with
external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals
•
8- and 16-bit port sizes with configuration for multiplexed or non-multiplexed address and data
buses
•
Byte-, word-, longword-, and 16-byte line-sized transfers
•
Programmable address-setup time with respect to the assertion of chip select
•
Programmable address-hold time with respect to the negation of chip select and transfer direction
11.1.3
Modes of Operation
The external interface is a configurable multiplexed bus set to one of the following modes:
11.2
External Signals
This section describes the external signals involved in data-transfer operations.
11.2.1
Address and Data Buses (FB_A[19:0], FB_D[7:0], FB_AD[
:0])
In non-multiplexed mode, the FB_A[19:0] and FB_D[7:0] buses carry the address and data, respectively.
•
Up to a 20-bit address (non-multiplexed) with 8-bit data
•
Up to a 20-bit address (multiplexed) with 16-bit data (write masking of upper/lower bytes not
supported)
•
Up to a 20-bit address (multiplexed) with 8-bit data
Table 11-1. Mini-FlexBus Signal Summary
Signal Name
I/O
Description
FB_A[19:0]
I/O
In a non-multiplexed configuration, this is the address bus. In a multiplexed
configuration this bus is the address/data bus, FB_AD[19:0].
FB_D[7:0]
I/O
In a non-multiplexed configuration, this is the data bus. In multiplexed
configurations, this bus is not used.
FB_CS[1:0]
O
General purpose chip-selects. In multiplexed mode, only FB_CS0 is
available. FB_CS1 is multiplexed with FB_ALE on a configurable package
pin.
FB_OE
O
Output enable
FB_R/W
O
Read/write. 1 = Read, 0 = Write
FB_ALE
O
Address latch enable. This signal is multiplexed with FB_CS1 on a
configurable package pin.
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