NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-20 Freescale Semiconductor
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as
debug control register 0x07 using the WDEBUG instruction and through the BDM port using the
WRITE_DREG command.
DRc: 0x07 (TDR) Access: Supervisor write-only
BDM write-only
Second Level Trigger
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W TRC L2EBL L2ED L2DI L2EA L2EPC L2PCI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
First Level Trigger
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W L2T L1T L1EBL L1ED L1DI L1EA L1EPC L1PCI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-9. Trigger Definition Register (TDR)
Table 20-14. TDR Field Descriptions
Field Description
31–30
TRC
Trigger response control. Determines how the processor responds to a completed trigger condition. The trigger
response is displayed on PST.
00 Display on PST only
01 Processor halt
10 Debug interrupt
11 Reserved
29
L2EBL
Enable level 2 breakpoint. Global enable for the breakpoint trigger.
0 Disables all level 2 breakpoints
1 Enables all level 2 breakpoint triggers
28–22
L2ED
Enable level 2 data breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on
the size and placement on the processor’s local data bus. Clearing all ED
bits disables data breakpoints.
TDR Bit Description
28 Data longword. Entire processor’s local data bus.
27 Lower data word.
26 Upper data word.
25 Lower lower data byte. Low-order byte of the low-order word.
24 Lower middle data byte. High-order byte of the low-order word.
23 Upper middle data byte. Low-order byte of the high-order word.
22 Upper upper data byte. High-order byte of the high-order word.