NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Mini-FlexBus
11-5 Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
11.3.3 Chip-Select Control Registers (CSCR0 – CSCR1)
Each CSCR n controls the auto-acknowledge, address setup and hold times, port size, and number of wait
states.
Table 11-4. CSMR n Field Descriptions
Field Description
31–16
BAM
Base address mask. Defines the chip-select block size by masking address bits. Setting a BAM bit causes the
corresponding CSAR bit to be a don’t care in the decode.
0 Corresponding address bit is used in chip-select decode.
1 Corresponding address bit is a don’t care in chip-select decode.
The block size for FB_CS n is 2
n
; n = (number of bits set in respective CSMR[BAM]) + 16.
For example, if CSAR0 equals 0x0040 and CSMR0[BAM] equals 0x000, FB_CS0 addresses two discontinuous
64 KB memory blocks: one from 0x40_0000 – 0x40_FFFF and one from 0x48_0000 – 0x48_FFFF.
Likewise, for FB_CS0 to access 2 MB of address space starting at location 0x40_0000, FB_CS1 must begin at the
next byte after FB_CS0 for a 1 MB address space. Therefore, CSAR0 equals 0x0040,
CSMR0[BAM] equals 0x001F, CSAR1 equals 0x0060, and CSMR1[BAM] equals 0x000F.
15–9 Reserved, must be cleared.
8
WP
Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the
range of addresses for which CSAR
n [WP] is set results in a bus error termination of the internal cycle and no external
cycle.
0 Read and write accesses are allowed
1 Only read accesses are allowed
7–1 Reserved, must be cleared.
0
V
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed
chip-selects do not assert until V bit is set. Reset clears each CSMR
n [V].
Note: At reset, no chip-select can be used until the CSMR0[V] is set. Afterward, FB_CS[1:0] functions as
programmed.
0 Chip-select invalid
1 Chip-select valid
Address: 0x08 (CSCR0)
0x14 (CSCR1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0 0 0
ASET RDAH WRAH
W
Reset: CSCR0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Reset: CSCR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WS MUX AA PS
0 0 0 0 0 0
W
Reset: CSCR0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 0
Reset: CSCR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-3. Chip-Select Control Registers (CSCR n )