Modes of Operation
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
3-13
SPI
x
Off
SoftNoClk
FullNoClk
SoftOn
FullOn
SoftOn
TPM
x
Off
SoftNoClk
FullNoClk
SoftOn
FullOn
SoftOn
Voltage Regulator / PMC
Partial
Shutdown.
1 kHz osc if
enabled
Soft Regulation.
1 kHz osc if
enabled
Full
Regulation
1 kHz osc on
SoftOn
1 kHz osc on
FullOn
1 kHz osc on
SoftOn
1 kHz osc on
1
This behavior is due to operation of the I/O cells in conjunction with the PMC. The Mini-FlexBus does not save state during
the transitions through stop2.
2
LP mode for the ADC is invoked by setting ADLPC. ADACK is selected by the ADCCFG[ADICLK] field in the ADC. See
Chapter 15, “Analog-to-Digital Converter (ADC12),”
for details.
3
LVD must be enabled to run in stop if converting the bandgap channel.
4
BLPE refers to the MCG bypassed external low-power state. See
Chapter 6, “Multipurpose Clock Generator (MCG)
,” for more
details.
5
The RESET/PTC3 pin also has a direct connection to the on-chip regulator wakeup input. Asserting this pin low while in stop2
triggers the PMC to wakeup. As a result, the device undergoes a power-on-reset sequence.
Table 3-5. Low-Power Mode Behavior (continued)
Peripheral
Mode
Stop2
Stop3
Stop4
LPwait
Wait
LPrun
