Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual,
Rev. 6
8-20
Freescale Semiconductor
vector numbers. The result is the conditional branch (PC = 0x5C8) is taken if there are no pending requests
or if the pending request is a level seven.
If there is a pending non-level seven request, execution continues with a three instruction sequence to
calculate and then branch to the appropriate alternate ISR entry point. This sequence assumes the
exception vector table is based at address 0x(00)00_0000 and that each ISR uses the same two-instruction
prologue shown here. The resulting alternate entry point is a fixed offset (8 bytes) from the normal entry
point defined in the exception vector table.
The ISR epilogue includes a three instruction sequence to restore the volatile registers from the stack and
return from the interrupt exception.
This example is intentionally simple, but does show how performing the software IACK and passing
control to an alternate entry point when there is a pending but masked interrupt request can avoid the
execution of the ISR epilogue, another interrupt exception, and the ISR prologue.
