Fast Ethernet Controller (FEC)
16-16
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
16.4.12 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields
used in transmission of a PAUSE frame. The opcode field is a constant value, 0x0001. When another node
detects a PAUSE frame, that node pauses transmission for the duration specified in the pause duration
field. The lower 16 bits of this register are not reset and you must initialize them.
16.4.13 Descriptor Individual Upper Address Register (IAUR)
IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address recognition
process uses this table to check for a possible match with the destination address (DA) field of receive
frames with an individual DA. This register is not reset and you must initialize it.
Offset: 0x0E8
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
PADDR2
TYPE
W
Reset — — — — — — — — — — — — — — — — 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
Figure 16-12. Physical Address Upper Register (PAUR)
Table 16-14. PAUR Field Descriptions
Field
Description
31–16
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address
field in PAUSE frames.
15–0
TYPE
Type field in PAUSE frames. These 16 read-only bits are a constant value of 0x8808.
Offset: 0x0EC
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
OPCODE
PAUSE_DUR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — —
Figure 16-13. Opcode/Pause Duration Register (OPD)
Table 16-15. OPD Field Descriptions
Field
Description
31–16
OPCODE
Opcode field used in PAUSE frames. These read-only bits are a constant, 0x0001.
15–0
PAUSE_DUR
Pause Duration field used in PAUSE frames.
