Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
8-13
NOTE
The requests associated with the INTC_FRC register have a fixed level and
priority that cannot be altered.
The INTC_PL6P7 register specifies the highest-priority, maskable interrupt request that is defined as the
level six, priority seven request. The INTC_PL6P6 register specifies the second-highest-priority, maskable
interrupt request defined as the level six, priority six request. Reset clears both registers, disabling any
request re-mapping.
For an example of the use of these registers, see
Section 8.6.2, “Using INTC_PL6P{7,6} Registers.”
8.3.4
INTC Wakeup Control Register (INTC_WCR)
The interrupt controller provides a combinatorial logic path to generate a special wakeup signal to exit
from the wait mode. The INTC_WCR register defines wakeup condition for interrupt recognition during
wait mode. This mode of operation works as follows:
1. Write to the INTC_WCR to enable this operation (set INTC_WCR[ENB]) and define the interrupt
mask level needed to force the core to exit wait mode (INTC_WCR[MASK]). The maximum value
of INTC_WCR[MASK] is 0x6 (0b110). The INTC_WCR is enabled with a mask level of 0 as the
default after reset.
2. Execute a stop instruction to place the processor into wait mode.
3. After the processor is stopped, the interrupt controller enables special logic that evaluates the
incoming interrupt sources in a purely combinatorial path; no clocked storage elements are
involved.
4. If an active interrupt request is asserted and the resulting interrupt level is greater than the mask
value contained in INTC_WCR[MASK], the interrupt controller asserts the wakeup output signal.
This signal is routed to the clock generation logic to exit the low-power mode and resume
processing.
Offset: CF1_INT 0x18 (INTC_PL6P7)
CF1_INT 0x19 (INTC_PL6P6)
Access: Read/Write
7
6
5
4
3
2
1
0
R
0
0
REQN
W
Reset
0
0
0
0
0
0
0
0
Figure 8-4. Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6})
Table 8-7. INTC_PL6P{7,6} Field Descriptions
Field
Description
7–6
Reserved, must be cleared.
5–0
REQN
Request number. Defines the peripheral IRQ number to be remapped as the level 6, priority 7 (for INTC_PL6P7)
request and level 6, priority 6 (for INTC_PL6P6) request.
Note:
The value must be a valid interrupt number. Unused or reserved interrupt numbers are ignored.
