Interrupt Controller (CF1_INTC)
MCF51CN128 Reference Manual,
Rev. 6
8-18
Freescale Semiconductor
disables interrupts. The ColdFire architecture defines seven interrupt levels, controlled by the 3-bit
interrupt priority mask field in the status register, SR[I], and the hardware automatically supports nesting
of interrupts.
To emulate the HCS08’s 1-level IRQ capabilities on V1 ColdFire, only two SR[I] settings are used:
•
Writing 0 to SR[I] enables interrupts.
•
Writing 7 to SR[I] disables interrupts.
The ColdFire core treats the level seven requests as non-maskable, edge-sensitive interrupts.
ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This
allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level
contained in the status register as the first instruction in the ISR. In addition, the V1 instruction set
architecture (ISA_C) includes an instruction (STLDSR) that stores the current interrupt mask level and
loads a value into the SR. This instruction is specifically intended for use as the first instruction of an
interrupt service routine that services multiple interrupt requests with different interrupt levels. For more
details see the
ColdFire Family Programmer’s Reference Manual
. A MOVE-to-SR instruction also
performs a similar function.
To emulate the HCS08’s 1-level IRQ nesting mechanisms, the ColdFire implementation enables interrupts
by clearing SR[I] (typically when using RTE to return to a process) and disables interrupts upon entering
every interrupt service routine by one of three methods:
1. Execution of STLDSR #0x2700 as the first instruction of an ISR.
2. Execution of MOVE.w #0x2700,SR as the first instruction of an ISR.
3. Static assertion of CPUCR[IME] that forces the processor to load SR[I] with seven automatically
upon the occurrence of an interrupt exception. Because this method removes the need to execute
multi-cycle instructions of #1 or #2, this approach improves system performance.
8.6.2
Using INTC_PL6P{7,6} Registers
Section 8.3.3, “INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}),”
describes
control registers that provide the ability to dynamically alter the request level and priority of two IRQs.
Specifically, these registers provide the ability to reassign two IRQs to be the highest level 6 (maskable)
requests. Consider the following example.
Suppose the system operation desires to remap the receive and transmit interrupt requests of a serial
communication device (SCI1) as the highest two maskable interrupts. The default assignments for the
SCI1 transmit and receive interrupts are:
•
sci1_rx = interrupt source 16 = vector 80 = level 4, priority 6
•
sci1_tx = interrupt source 17 = vector 81 = level 4, priority 5
To remap these two requests, the INTC_PL6P{7,6} registers are programmed with the desired interrupt
source number:
•
Setting INTC_PL6P7 to 16 (0x10), remaps sci1_rx as level 6, priority 7.
•
Setting INTC_PL6P6 to 17 (0x11), remaps sci1_tx as level 6, priority 6.
