Device Overview
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
1-11
Bypassed Low Power External (BLPE) MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC).
The PLL and FLL are disabled, and MCGLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to one
of the bypassed external mode.
STOP
Entered whenever the MCU enters a Stop state. The FLL and PLL are
disabled, and all MCG clock signals are static except in the following
cases:
• MCGIRCLK can be active in Stop mode under certain conditions.
Table 1-6. MCG Modes (continued)
Mode
Description
