Multipurpose Clock Generator (MCG)
MCF51CN128 Reference Manual, Rev. 6
6-12
Freescale Semiconductor
Table 6-10. MCG Modes of Operation
Mode
Related field values
Description
FLL Engaged
Internal (FEI)
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 00
• MCGC3[PLLS] = 0
Default. MCGOUT is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL clock frequency locks to 1024 times
the internal reference frequency. MCGLCLK is derived from the FLL, and
the PLL is disabled in a low-power state.
FLL Engaged
External (FEE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC1[RDIV] is programmed
to divide the reference clock to
be within the range of 31.2500
to 39.0625 kHz.
• MCGC3[PLLS] = 0
MCGOUT is derived from the FLL clock, which is controlled by the
external reference clock. The external reference clock that is enabled
can be produced by an external crystal, ceramic resonator, or another
external clock source connected to the required crystal oscillator
(XOSC). The FLL clock frequency locks to 1024 times the external
reference frequency, as specified by MCGC1[RDIV], MCGC2[RANGE],
and MCGC3[DIV32]. MCGLCLK is derived from the FLL, and the PLL is
disabled in a low-power state.
FLL Bypassed
Internal (FBI)
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 01
• MCGC2[LP] = 0 (or the BDM is
enabled)
• MCGC3[PLLS] = 0
MCGOUT is derived from the internal reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while the MCGOUT clock is driven
from the internal reference clock.
MCGOUT is derived from the internal reference clock. The FLL clock is
controlled by the internal reference clock, and the FLL clock frequency
locks to 1024 times the internal reference frequency. MCGLCLK is
derived from the FLL, and the PLL is disabled in a low-power state.
FLL Bypassed
External (FBE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• MCGC1[RDIV] is programmed
to divide the reference clock to
be within the range of 31.2500
to 39.0625 kHz
• MCGC2[LP] = 0 (or the BDM is
enabled)
• MCGC3[PLLS] = 0
MCGOUT is derived from the external reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while MCGOUT is driven from the
external reference clock.
MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC).The FLL clock is controlled by the
external reference clock, and the FLL clock frequency locks to 1024
times the external reference frequency, as selected by MCGC1[RDIV],
MCGC2[RANGE], and MCGC3[DIV32]. MCGLCLK is derived from the
FLL, and the PLL is disabled in a low-power state.
PLL Engaged
External (PEE)
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC1[RDIV] is programmed
to divide the reference clock to
be within the range of 1 to
2 MHz.
• PLLS = 1
MCGOUT is derived from the PLL clock, which is controlled by the
external reference clock. The external reference clock that is enabled
can be produced by an external crystal, ceramic resonator, or another
external clock source connected to the required crystal oscillator
(XOSC). The PLL clock frequency locks to a multiplication factor, as
specified by MCGC3[VDIV], times the external reference frequency, as
specified by MCGC1[RDIV], MCGC2[RANGE], and MCGC3[DIV32]. If
the BDM is enabled, MCGLCLK is derived from the DCO (open-loop
mode) divided by two. If the BDM is not enabled, the FLL is disabled in a
low-power state.
