Fast Ethernet Controller (FEC)
Freescale Semiconductor
16-13
MCF51CN128 Reference Manual, Rev. 6
16.4.8
Receive Control Register (RCR)
RCR controls the operational mode of the receive block and must be written only when ECR[ETHER_EN]
is cleared (initialization time).
Table 16-10. Programming Examples for MSCR
Internal FEC Clock
Frequency
MSCR[MII_SPEED]
FEC_MDC frequency
25 MHz
0x5
2.50 MHz
33 MHz
0x7
2.36 MHz
40 MHz
0x8
2.50 MHz
50 MHz
0xA
2.50 MHz
66 MHz
0xE
2.36 MHz
Offset: 0x084
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
MAX_FL
W
Reset
0
0
0
0
0
1
0
1
1
1
1
0
1
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
FCE
BC_
REJ
PROM
MII_
MODE
DRT LOOP
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Figure 16-9. Receive Control Register (RCR)
Table 16-11. RCR Field Descriptions
Field
Description
31–27
Reserved, must be cleared.
26–16
MAX_FL
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the
end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive frames longer
than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor.
The recommended default value to be programmed is 1518 or 1522 if VLAN tags are supported.
15–6
Reserved, must be cleared.
5
FCE
Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter
stops transmitting data frames for a given duration.
4
BC_REJ
Broadcast frame reject. If asserted, frames with DA (destination address) equal to FFFF_FFFF_FFFF are rejected
unless the PROM bit is set. If BC_REJ and PROM are set, frames with broadcast DA are accepted and the M
(MISS) is set in the receive buffer descriptor.
3
PROM
Promiscuous mode. All frames are accepted regardless of address matching.
