Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
17-10
Freescale Semiconductor
17.3.6
IIC Data I/O Register (IICD)
NOTE
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for
the transmission to begin. For example, if the IIC is configured for master transmit but a master receive is
desired, then reading the IICD does not initiate the receive.
1
IICIF
IIC Interrupt Flag
— The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
•
One byte transfer including ACK/NACK bit completes if FACK = 0
•
One byte transfer including ACK/NACK bit completes if FACK = 1 and this byte is an address byte
•
One byte transfer excluding ACK/NCAK bit completes if FACK = 1 and this byte is a data byte. an ACK or
NACK is sent out on the bus by writing 0 or 1 to TXAK after this bit is set.
•
Match of slave addresses to calling address (Primary Slave address, General Call address, Alert
Response address, and Second Slave address) (Received address is stored in data register)
•
Arbitration lost
•
Timeouts in SMBus mode except high timeout
0 No interrupt pending.
1 Interrupt pending.
0
RXAK
Receive Acknowledge
— When the RXAK bit is low, it indicates an acknowledge signal is received after the
completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received.
1 No acknowledge received.
7
6
5
4
3
2
1
0
R
DATA
W
Reset
0
0
0
0
0
0
0
0
Figure 17-6. IIC Data I/O Register (IICD)
Table 17-7. IICD Field Descriptions
Field
Description
7:0
DATA
Data
— In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Table 17-6. IICS Field Descriptions (continued)
Field
Description
