NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
17-8 Freescale Semiconductor
17.3.4 IIC Control Register (IICC1)
7 6 5 4 3 2 1 0
R
IICEN IICIE MST TX TXAK RSTA
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 17-4. IIC Control Register (IICC1)
Table 17-5. IICC1 Field Descriptions
Field Description
7
IICEN
IIC Enable — The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled.
1 IIC is enabled.
6
IICIE
IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
5
MST
Master Mode Select — When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave mode.
1 Master mode.
4
TX
Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
3
TXAK
Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
The following two conditions effect NAK/ACK generation.
If FACK (fast NACK/ACK) is cleared,
0 An acknowledge signal is sent out to the bus on the following receiving data byte.
1 No acknowledge signal response is sent to the bus on the following receiving data byte.
If FASK bit is set. no ACK or NACK is sent out after receiving one data byte until this TXAK bit is written
0 An acknowledge signal is sent out to the bus on the current receiving data byte
1 No acknowledge signal response is sent to the bus on the current receiving data byte
Note: SCL is held to low until TXAK is written.
2
RSTA
(Write Only
read always
0)
Repeat START — Writing a 1 to this bit generates a repeated START condition provided it is the current master.
Attempting a repeat at the wrong time results in loss of arbitration.
0 No repeat start detected in bus operation.
1 Repeat start generated.