Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-23
valid bit. These registers’ contents are compared with the processor’s program counter register when TDR
is configured appropriately.
The PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and
through the BDM port using the WRITE_DREG command using values shown in
NOTE
Version 1 ColdFire core devices implement a 24-bit, 16 MB address map.
When programming these registers with a 32-bit address, the upper byte
must
be zero-filled.
shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and
via the BDM port using the WRITE_DREG command. PBMR only masks PBR0.
DRc: 0x08 (PBR0)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Address
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 20-10. Program Counter Breakpoint Register 0 (PBR0)
Table 20-15. PBR0 Field Descriptions
Field
Description
31–0
Address
PC breakpoint address. The address to be compared with the PC as a breakpoint trigger. Because all instruction
sizes are multiples of 2 bytes, bit 0 of the address should always be zero.
DRc: 0x18 (PBR1)
0x1A (PBR2)
0x1C (PBR3)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Address
V
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0
Figure 20-11. Program Counter Breakpoint Register
n
(PBR
n, n = 1,2,3
)
Table 20-16. PBR
n
Field Descriptions
Field
Description
31–1
Address
PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint trigger.
0
V
Valid bit. This bit must be set for the PC breakpoint to occur at the address specified in the Address field.
0 PBR is disabled.
1 PBR is enabled.
