Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
5-23
5.7.12
System Clock Gating Control 3 Register (SCGC3)
This register contains control bits to enable or disable the bus clock to the PTA-H modules. Gating off the
clocks to unused peripherals reduces the microcontroller’s run and wait currents. See
for more information.
5.7.13
System Clock Gating Control 4 Register (SCGC4)
This register contains control bits to enable or disable the bus clock to MTIM2, Port Mux Control, the
Mini-FlexBus and Fast Ethernet Controller (FEC) modules and PTJ. Gating off the clocks to unused
7
6
5
4
3
2
1
0
R
PTH
PTG
PTF
PTE
PTD
PTC
PTB
PTA
W
Reset:
_
1
1
1 in 80-pin package, 0 in 48-pin and 64-pin packages
_
2
2
1 in 80-pin and 64-pin packages, 0 in 48-pin package
_
2
1
1
1
1
1
Figure 5-13. System Clock Gating Control 3 Register (SCGC3)
Table 5-18. SCGC3 Register Field Descriptions
Field
Description
7
PTH
PTH Clock Gate Control
0 Bus clock to the PTH module is disabled.
1 Bus clock to the PTH module is enabled.
6
PTG
PTG Clock Gate Control
0 Bus clock to the PTG module is disabled.
1 Bus clock to the PTG module is enabled.
5
PTF
PTF Clock Gate Control
0 Bus clock to the PTF(RGPIO) module is disabled.
1 Bus clock to the PTF(RGPIO) module is enabled.
4
PTE
PTE Clock Gate Control
0 Bus clock to the PTE module is disabled.
1 Bus clock to the PTE module is enabled.
3
PTD
PTD Clock Gate Control
0 Bus clock to the PTD module is disabled.
1 Bus clock to the PTD module is enabled.
2
PTC
PTC Clock Gate Control
0 Bus clock to the PTC module is disabled.
1 Bus clock to the PTC module is enabled.
1
PTB
PTB Clock Gate Control
0 Bus clock to the PTB module is disabled.
1 Bus clock to the PTB module is enabled.
0
PTA
PTA Clock Gate Control
0 Bus clock to the PTA module is disabled.
1 Bus clock to the PTA module is enabled.
