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NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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MCF51CN128 Reference Manual, Rev. 6

xiv

Freescale Semiconductor

 

16.5.15Ethernet Error-Managing Procedure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-38

16.5.15.1 Transmission Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-39
16.5.15.2 Reception Errors   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16-39

Chapter 17 

Inter-Integrated Circuit (IIC)

17.1 Introduction   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-1

17.1.1 Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-2
17.1.2 Modes of Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-2
17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-3

17.2 External Signal Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-3

17.2.1 SCL — Serial Clock Line  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-3
17.2.2 SDA — Serial Data Line  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-3

17.3 Register Definition  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-4

17.3.1 Module Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-4
17.3.2 IIC Address Register 1 (IICA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-4
17.3.3 IIC Frequency Divider Register (IICF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-5
17.3.4 IIC Control Register (IICC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-8
17.3.5 IIC Status Register (IICS)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-9
17.3.6 IIC Data I/O Register (IICD)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-10
17.3.7 IIC Control Register 2 (IICC2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-12
17.3.8 IIC SMBus Control and Status Register (IICSMB) . . . . . . . . . . . . . . . . . . . . . . . . . .  17-13
17.3.9 IIC Address Register 2 (IICA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-14
17.3.10IIC SCL Low Time Out Register High (IICSLTH)  . . . . . . . . . . . . . . . . . . . . . . . . . .  17-14
17.3.11IIC SCL LowTime Out register Low (IICSLTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-14
17.3.12IIC Programmable Input Glitch Filter (IICFLT)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-15

17.4 Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-16

17.4.1 IIC Protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-16

17.4.1.1 START Signal  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-17
17.4.1.2 Slave Address Transmission  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-17
17.4.1.3 Data Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-17
17.4.1.4 STOP Signal   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-18
17.4.1.5 Repeated START Signal  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-18
17.4.1.6 Arbitration Procedure   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-18
17.4.1.7 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-18
17.4.1.8 Handshaking   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-19
17.4.1.9 Clock Stretching   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-19

17.4.2 10-bit Address  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-20

17.4.2.1 Master-Transmitter Addresses a Slave-Receiver . . . . . . . . . . . . . . . . . . . . .  17-20
17.4.2.2 Master-Receiver Addresses a Slave-Transmitter . . . . . . . . . . . . . . . . . . . . .  17-20

17.4.3 Address Matching   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-21
17.4.4 System Management Bus Specification   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-21

17.4.4.1 Timeouts   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-21
17.4.4.2 FAST ACK and NACK  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-23

17.5 Resets  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17-23

Summary of Contents for freescale semiconductor ColdFire MCF51CN128 Series

Page 1: ...MCF51CN128 ColdFire Integrated Microcontroller Reference Manual Devices Supported MCF51CN128 Document Number MCF51CN128RM Rev 6 12 2009...

Page 2: ...does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequ...

Page 3: ...tion Diagram 1 8 1 4 2 System Clocks 1 9 1 4 3 Clock Gating 1 9 1 4 4 MCG Modes of Operation 1 10 1 4 5 MCG Mode State Diagram 1 12 Chapter 2 Pins and Connections 2 1 Package Pin Assignments 2 1 2 1 1...

Page 4: ...signments 4 5 4 2 1 Flash Module Reserved Memory Locations 4 22 4 3 RAM 4 23 4 4 Flash Memory 4 24 4 4 1 Features 4 24 4 4 2 Register Descriptions 4 25 4 4 2 1 Flash Clock Divider Register FCDIV 4 25...

Page 5: ...System Power Management Status and Control 2 Register SPMSC2 5 18 5 7 9 System Power Management Status and Control 3 Register SPMSC3 5 19 5 7 10 System Clock Gating Control 1 Register SCGC1 5 21 5 7...

Page 6: ...Map Register Description 7 2 7 2 1 Data Registers D0 D7 7 3 7 2 2 Address Registers A0 A6 7 4 7 2 3 Supervisor User Stack Pointers A7 and OTHER_A7 7 4 7 2 4 Condition Code Register CCR 7 5 7 2 5 Prog...

Page 7: ...2 Force Interrupt Register INTC_FRC 8 11 8 3 3 INTC Programmable Level 6 Priority 7 6 Registers INTC_PL6P 7 6 8 12 8 3 4 INTC Wakeup Control Register INTC_WCR 8 13 8 3 5 INTC Set Interrupt Force Regis...

Page 8: ...tors 9 11 9 5 1 4 Keyboard Interrupt Initialization 9 11 9 5 2 Keyboard Programming Model 9 11 9 5 2 1 KBIx Interrupt Status and Control Register KBIxSC 9 12 9 5 2 2 KBIx Interrupt Pin Select Register...

Page 9: ...4 11 3 3 Chip Select Control Registers CSCR0 CSCR1 11 5 11 4 Functional Description 11 7 11 4 1 Chip Select Operation 11 7 11 4 1 1 General Chip Select Operation 11 7 11 4 1 2 8 and 16 Bit Port Sizing...

Page 10: ...CIxC1 13 7 13 2 3 SCI Control Register 2 SCIxC2 13 8 13 2 4 SCI Status Register 1 SCIxS1 13 9 13 2 5 SCI Status Register 2 SCIxS2 13 11 13 2 6 SCI Control Register 3 SCIxC3 13 12 13 2 7 SCI Data Regis...

Page 11: ...3 14 5 3 Mode Fault Detection 14 14 Chapter 15 Analog to Digital Converter ADC12 15 1 Introduction 15 1 15 1 1 ADC Clock Gating 15 1 15 1 2 Module Configurations 15 1 15 1 2 1 Channel Assignments 15 1...

Page 12: ...Module Initialization Example 15 17 15 5 1 1 Initialization Sequence 15 17 15 5 1 2 Pseudo Code Example 15 17 15 6 Application Information 15 19 15 6 1 External Pins and Routing 15 19 15 6 1 1 Analog...

Page 13: ...4 17Transmit FIFO Watermark Register TFWR 16 18 16 4 18FIFO Receive Bound Register FRBR 16 19 16 4 19FIFO Receive Start Register FRSR 16 19 16 4 20Receive Descriptor Ring Start Register ERDSR 16 20 16...

Page 14: ...2 17 3 8 IIC SMBus Control and Status Register IICSMB 17 13 17 3 9 IIC Address Register 2 IICA2 17 14 17 3 10IIC SCL Low Time Out Register High IICSLTH 17 14 17 3 11IIC SCL LowTime Out register Low II...

Page 15: ...r MTIMSC 18 5 18 3 2 MTIM Clock Configuration Register MTIMCLK 18 6 18 3 3 MTIM Counter Register MTIMCNT 18 7 18 3 4 MTIM Modulo Register MTIMMOD 18 7 18 4 Functional Description 18 8 18 4 1 MTIM Oper...

Page 16: ...es of Operations 20 3 20 2 External Signal Descriptions 20 5 20 3 Memory Map Register Definition 20 6 20 3 1 Configuration Status Register CSR 20 7 20 3 2 Extended Configuration Status Register XCSR 2...

Page 17: ...re Handshake Abort Procedure 20 53 20 4 2 Real Time Debug Support 20 56 20 4 3 Trace Support 20 56 20 4 3 1 Begin Execution of Taken Branch PST 0x05 20 58 20 4 3 2 PST Trace Buffer PSTB Entry Format 2...

Page 18: ...g This section lists additional reading that provides background for the information in this manual as well as general information about ColdFire architecture General Information Useful information ab...

Page 19: ...alics indicate variable command parameters Book titles in text are set in italics 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG FIELD Abbreviations for registers are s...

Page 20: ...are always read as zeros W R 1 Indicates a reserved bit field in a memory mapped register These bits are always read as ones W R FIELDNAME Indicates a read write bit W R FIELDNAME Indicates a read onl...

Page 21: ...BASE T TX fast ethernet controller FEC with media independent interface MII to connect an external physical transceiver PHY Multi function external bus interface Mini FlexBus A collection of communica...

Page 22: ...puter operating properly Yes IIC1 inter integrated circuit Yes IIC2 Yes IRQ interrupt request input Yes KBI keyboard interrupts 16 12 6 LVD low voltage detector Yes MCG multipurpose clock generator Ye...

Page 23: ...view MCF51CN128 Reference Manual Rev 6 Freescale Semiconductor 1 3 1 2 MCF51CN128 Series Block Diagram 1 2 1 Block Diagram Figure 1 1 shows the connections between the MCF51CN128 series pins and funct...

Page 24: ...SDA2 PTA0 PHYCLK PTA6 MII_RXD0 MISO2 PTA7 MII_RX_DV MOSI2 VDDA VREFH VSSA VREFL SPI1 SCI2 MCG VREG SIM ColdFire V1 core Port D EXTAL XTAL Port D RXD2 TXD2 Port C SS1 SPSCK1 MOSI1 MISO1 IIC2 Port C G S...

Page 25: ...t capabilities LVD low voltage detect Provides an interrupt to the CF1CORE in the event that the supply voltage drops below a critical value The LVD can also be programmed to reset the device upon a l...

Page 26: ...ter ADC12 1 Fast Ethernet Controller FEC General Purpose I O GPIO 2 Inter Integrated Circuit IIC 3 Interrupt Controller CF1_INTC 1 Keyboard Interrupt KBI 2 Low Power Oscillator OSCVLP_25MHz 1 Mini Fle...

Page 27: ...ColdFire core see Chapter 7 ColdFire Core 1 3 1 User Programming Model Figure 1 2 illustrates the integer portion of the user programming model It consists of the following registers 16 general purpos...

Page 28: ...IM Internal Peripheral Select Register SIMIPS for details MCG Notes 1 The ADC has minimum and maximum frequency requirements See the Chapter 15 Analog to Digital Converter ADC12 and the MCF51CN128 Dat...

Page 29: ...ow frequency DCO digitally controlled oscillator Development tools can select this internal self clocked source to speed up BDC communications in systems where the bus clock is slow Please see Figure...

Page 30: ...L Bypassed External FBE MCGOUT is derived from the external reference clock the FLL is operational but its output clock is not used This mode is useful to allow the FLL to acquire its target frequency...

Page 31: ...al clock source connected to the required crystal oscillator XOSC The PLL and FLL are disabled and MCGLCLK is not available for BDC communications If the BDM becomes enabled the mode switches to one o...

Page 32: ...bus frequency is less than 125 kHz and the FLLs are disengaged prior to switching to BLPE and BLPI modes of operation Figure 1 4 MCG Mode State Diagram Entered from any state when MCU enters stop Retu...

Page 33: ...ns and Connections This section describes signals that connect to package pins It includes pinout diagrams recommended system connections and detailed discussions of signals 2 1 Package Pin Assignment...

Page 34: ...MII_TXD3 TPM2CH2 PTC1 MII_COL SCL1 PTC2 MII_CRS SDA1 RESET PTC3 PTF4 RGPIO12 FB_D5 TMRCLK2 PTF5 RGPIO13 FB_D4 TPM2CH0 PTF6 RGPIO14 FB_A14 FB_AD14 TPM2CH1 PTF7 RGPIO15 FB_A13 FB_AD13 TPM2CH2 PTH4 FB_A...

Page 35: ...0 MII_TXD3 TPM2CH2 PTC1 MII_COL SCL1 PTC2 MII_CRS SDA1 RESET PTC3 PTF4 RGPIO12 FB_D5 TMRCLK2 PTF5 RGPIO13 FB_D4 TPM2CH0 PTF6 RGPIO14 FB_A14 FB_AD14 TPM2CH1 PTF7 RGPIO15 FB_A13 FB_AD13 TPM2CH2 48 47 46...

Page 36: ...DP8 PTD0 RGPIO0 TXD1 ADP7 VDDA VSS4 PTE5 KBI2P5 IRQ TPM1CH2 BKGD MS PTD6 RGPIO6 PTD5 RGPIO5 XTAL PTD4 RGPIO4 EXTAL PTD3 RGPIO3 RXD2 ADP4 PTA4 MII_RXD2 RXD3 PTA5 MII_RXD1 SPSCK2 PTA6 MII_RXD0 MISO2 PTB...

Page 37: ...ir input pins and peripheral clocks disabled by default The mux controls for keyboard 1 and the Mini FlexBus must not be programmed to those functions unless supported on the package in question 1 Por...

Page 38: ...iode to VDD DSE and SRE port controls for this bit have no effect 33 29 PTF4 RGPIO12 FB_D5 TMRCLK2 RGPIO_ENB selects between standard GPIO and RGPIO 34 30 PTF5 RGPIO13 FB_D4 TPM2CH0 35 31 PTF6 RGPIO14...

Page 39: ...SS4 63 51 39 PTD4 RGPIO4 EXTAL RGPIO_ENB selects between standard GPIO and RGPIO 64 52 40 PTD5 RGPIO5 XTAL 65 53 41 BKGD MS PTD6 RGPIO 6 This pin has an internal pullup PTD6 RGPIO6 can only be program...

Page 40: ...7 SPSCK2 ADP3 RGPIO_ENB selects between standard GPIO and RGPIO 67 55 43 PTE0 KBI2P0 MISO2 ADP2 68 56 44 PTE1 KBI2P1 MOSI2 ADP1 69 57 45 PTE2 KBI2P2 SS2 ADP0 70 58 46 PTE3 KBI2P3 TPM1CH0 71 59 47 PTE4...

Page 41: ...R 9 9 9 PTA6 PTA6 MII_RXD0 MISO2 MII_RXD0 8 8 8 PTA5 PTA5 MII_RXD1 SPSCK2 MII_RXD1 7 7 7 PTA4 PTA4 MII_RXD2 RXD3 MII_RXD2 6 6 6 PTA3 PTA3 MII_RXD3 TXD3 MII_RXD3 24 20 16 PTB3 PTB3 MII_TX_CLK MOSI1 MII...

Page 42: ...I1P3 PTG3 KBI1P3 FB_A5 FB_AD5 SDA1 FB_A5 FB_AD5 55 47 PTG2 KBI1P2 PTG2 KBI1P2 FB_A6 FB_AD6 SCL1 FB_A6 FB_AD6 54 46 PTG1 KBI1P1 PTG1 KBI1P1 FB_A7 FB_AD7 SDA2 FB_A7 FB_AD7 53 45 PTG0 KBI1P0 PTG0 KBI1P0...

Page 43: ...C6 PTC6 SCL2 MISO1 ADP9 SCL2 54 46 PTG1 KBI1P1 PTG1 KBI1P1 FB_A7 FB_AD7 SD A2 SDA2 5 5 5 PTA2 PTA2 MII_MDC SCL2 SDA2 48 40 32 PTC7 PTC7 SDA2 SPSCK1 ADP8 SDA2 Table 2 7 SPI1 Pinout Summary 80 Pin 64 Pi...

Page 44: ...ble 2 10 SCI2 Pinout Summary 80 Pin 64 Pi n 48 Pin Default Function Signals SCI12 52 44 36 PTD3 RGPIO3 PTD3 RGPIO3 RXD2 ADP4 RXD2 51 43 35 PTD2 RGPIO2 PTD2 RGPIO2 TXD2 ADP5 TXD2 Table 2 11 SCI3 Pinout...

Page 45: ...TPM2CH1 TPM2CH1 35 31 PTF6 RGPIO1 4 PTF6 RGPIO14 FB_A14 FB_AD14 TPM2C H1 TPM2CH1 28 24 20 PTB7 PTB7 MII_TXD2 TPM2CH1 TPM2CH1 36 32 PTF7 RGPIO1 5 PTF7 RGPIO15 FB_A13 FB_AD13 TPM2C H2 TPM2CH2 40 PTH7 PT...

Page 46: ...4 4 PTA1 PTA1 MII_MDIO SDA2 PTA1 5 5 5 PTA2 PTA2 MII_MDC SCL2 PTA2 6 6 6 PTA3 PTA3 MII_RXD3 TXD3 PTA3 7 7 7 PTA4 PTA4 MII_RXD2 RXD3 PTA4 8 8 8 PTA5 PTA5 MII_RXD1 SPSCK2 PTA5 9 9 9 PTA6 PTA6 MII_RXD0 M...

Page 47: ...1 69 57 45 PTE2 KBI2P2 PTE2 KBI2P2 SS2 ADP0 PTE2 70 58 46 PTE3 KBI2P3 PTE3 KBI2P3 TPM1CH0 PTE3 71 59 47 PTE4 KBI2P4 PTE4 KBI2P4 CLKOUT TPM1CH1 PTE4 72 60 48 PTE5 KBI2P5 PTE5 KBI2P5 IRQ TPM1CH2 PTE5 73...

Page 48: ...H4 38 PTH5 PTH5 FB_A11 FB_AD11 PTH5 39 PTH6 PTH6 FB_A10 FB_AD10 TPM2CH1 PTH6 40 PTH7 PTH7 FB_A9 FB_AD9 TPM2CH2 PTH7 75 63 PTJ0 PTJ0 FB_CS1 FB_ALE PTJ0 76 64 PTJ1 PTJ1 FB_A4 FB_AD4 PTJ1 77 PTJ2 PTJ2 FB...

Page 49: ...6 PTE6 KBI2P6 FB_D0 TXD3 KBI2P6 74 62 PTE7 KBI2P7 PTE7 KBI2P7 FB_CS0 RXD3 KBI2P7 Table 2 19 RGPIO Pinout Summary 80 Pin 64 Pin 48 Pin Default Function Signals RGPIO 49 41 33 PTD0 RGPIO0 PTD0 RGPIO0 TX...

Page 50: ...s 0x01 etc 63 51 39 PTD4 RGPIO4 PTD4 RGPIO4 EXTAL RGPIO4 64 52 40 PTD5 RGPIO5 PTD5 RGPIO5 XTAL RGPIO5 65 53 41 BKGD MS BKGD MS PTD6 RGPIO6 RGPIO6 66 54 42 PTD7 RGPIO7 PTD7 RGPIO7 SPSCK2 ADP3 RGPIO7 13...

Page 51: ...F7 F6 F5 F4 0x FF FF_80C B MC PTFPF2 F3 F2 F1 F0 0x FF FF_80C C MC PTGPF1 G7 G6 G5 G4 0x FF FF_80C D MC PTGPF2 G3 G2 G1 G0 0x FF FF_80C E MC PTHPF1 H7 H6 H5 H4 0x FF FF_80C F MC PTHPF2 H3 H2 H1 H0 0x...

Page 52: ...erved 11 Reserved Port PTA1 Pin Mux Controls 00 PTA1 01 MII_MDIO 10 Reserved 11 SDA2 Port PTA2 Pin Mux Controls 00 PTA2 01 MII_MDC 10 Reserved 11 SCL2 Port PTA3 Pin Mux Controls 00 PTA3 01 MII_RXD3 10...

Page 53: ...MII_RX_CLK 10 SS2 11 Reserved Port PTB1 Pin Mux Controls 00 PTB1 01 MII_RX_ER 10 Reserved 11 TMRCLK1 Port PTB2 Pin Mux Controls 00 PTB2 01 MII_TX_ER 10 SS1 11 Reserved Port PTB3 Pin Mux Controls 00 P...

Page 54: ...PTB7 Pin Mux Controls 00 PTB7 01 MII_TXD2 10 Reserved 11 TPM2CH1 Port PTC0 Pin Mux Controls 00 PTC0 01 MII_TXD3 10 Reserved 11 TPM2CH2 Port PTC1 Pin Mux Controls 00 PTC1 01 MII_COL 10 Reserved 11 SCL...

Page 55: ...d 10 MOSI1 11 ADP10 Port PTC6 Pin Mux Controls 00 PTC6 01 SCL2 10 MISO1 11 ADP9 Port PTC7 Pin Mux Controls 00 PTC7 01 SDA2 10 SPSCK1 11 ADP8 Port PTD0 Pin Mux Controls 00 PTD0 RGPIO0 01 Reserved 10 TX...

Page 56: ...00 PTD4 RGPIO4 01 Reserved 10 Reserved 11 EXTAL Port PTD5 Pin Mux Controls 00 PTD5 RGPIO5 01 Reserved 10 Reserved 11 XTAL Port PTD6 Pin Mux Controls 00 BKGD MS 01 PTD6 RGPIO6 10 Reserved 11 Reserved...

Page 57: ...SS2 11 ADP0 Port PTE3 Pin Mux Controls 00 PTE3 01 KBI2P3 10 Reserved 11 TPM1CH0 Port PTE4 Pin Mux Controls 00 PTE4 01 KBI2P4 10 CLKOUT 11 TPM1CH1 Port PTE5 Pin Mux Controls 00 PTE5 01 KBI2P5 10 IRQ 1...

Page 58: ...A18 FB_AD18 11 Reserved Port PTF2 Pin Mux Controls 00 PTF2 RGPIO10 01 Reserved 10 FB_A17 FB_AD17 11 Reserved Port PTF3 Pin Mux Controls 00 PTF3 RGPIO11 01 Reserved 10 FB_A16 FB_AD16 11 Reserved Port P...

Page 59: ...1 TPM2CH2 Port PTG0 Pin Mux Controls 00 PTG0 01 KBI1P0 10 FB_A8 FB_AD8 11 SCL2 Port PTG1 Pin Mux Controls 00 PTG1 01 KBI1P1 10 FB_A7 FB_AD7 11 SDA2 Port PTG2 Pin Mux Controls 00 PTG2 01 KBI1P2 10 FB_A...

Page 60: ...0 FB_D2 11 Reserved Port PTG7 Pin Mux Controls 00 PTG7 01 KBI1P7 10 FB_D1 11 Reserved Port PTH0 Pin Mux Controls 00 PTH0 01 Reserved 10 FB_A15 FB_AD15 11 Reserved Port PTH1 Pin Mux Controls 00 PTH1 01...

Page 61: ...ls 00 PTH5 01 Reserved 10 FB_A11 FB_AD11 11 Reserved Port PTH6 Pin Mux Controls 00 PTH6 01 Reserved 10 FB_A10 FB_AD10 11 TPM2CH1 Port PTH7 Pin Mux Controls 00 PTH7 01 Reserved 10 FB_A9 FB_AD9 11 TPM2C...

Page 62: ...to BDM_RESET in the ColdFire XCSR register with MS low after issuing BDM command 2 RESET PTC3 features an optional internal pullup device 3 RC filter on RESET PTC3 pin recommended for noisy environmen...

Page 63: ...KBI2P3 TPM1CH0 PTE4 KBI2P4 CLKOUT TPM1CH1 PTE5 KBI2P5 IRQ TPM1CH2 PTE6 KBI2P6 FB_D0 TXD3 PTE7 KBI2P7 FB_CS0 RXD3 PORT H PTH0 FB_A15 FB_AD15 PTH1 FB_OE PTH2 FB_D7 TMRCLK1 PTH3 FB_D6 TPM2CH0 PTH4 FB_A1...

Page 64: ...ernally generated clock provided by the multipurpose clock generation MCG module The oscillator XOSC in this microcontroller is a Pierce oscillator that can accommodate a crystal or ceramic resonator...

Page 65: ...his pin See Figure 2 4 for an example When any reset is initiated whether from an external source or from an internal source the RESET pin is driven low for approximately 66 bus cycles and released Th...

Page 66: ...ort up to 70 general purpose I O pins1 which are shared with on chip peripheral functions timers serial I O ADC etc When a port pin is configured as a general purpose output or a peripheral uses the p...

Page 67: ...nd to clear security which involves mass erasing the on chip flash memory No other CPU access is allowed Secure mode can be used in conjunction with each of the power modes below Run mode CPU clocks c...

Page 68: ...n be programmed to occur naturally as a result of a STOP instruction Additionally standby mode can be explicitly invoked by the SPMSC2 LPR bit Use of standby is limited to bus frequencies less than 12...

Page 69: ...Hz peripheral clock frequency x x 0 0 x 1 0 Low freq required MCG in BLPE mode Loose Reg 0 1 0 Wait mode processor clock nominally inactive but peripherals are clocked x 1 x x x 0 x Periph clocks on C...

Page 70: ...CSR ENBDM forced stop4 to occur in its place 1 Stated another way if XCSR ENBDM has been set via the BDM interface then the power management controller keeps or puts the regulator in full regulation d...

Page 71: ...p2 Pre configure settings shown in Table 3 2 execute STOP instruction Stop2 Run Assert RESET PTC31 low or RTC timeout Reload environment from RAM 3 LPrun LPwait Pre configure settings shown in Table 3...

Page 72: ...re Debug CF1_DEBUG for more details regarding the debug interface 3 5 Secure Mode While the MCU is in secure mode there are severe restrictions on which debug commands can be used In this mode only th...

Page 73: ...re details The bus frequency is less than 125 kHz The ADC is in low power mode ADCCFG ADLPC 1 or disabled Low voltage detect is disabled The LVDE and or LVDSE bit in SPMSC1 register is cleared Flash p...

Page 74: ...service routine 3 7 2 Low Power Wait Mode LPwait Low power wait mode is entered by executing a STOP instruction while the MCU is in low power run mode and configured as shown in Table 3 2 In the low...

Page 75: ...wait mode The BACKGROUND command can wake the MCU from stop4 and enter halt mode if XCSR ENBDM was set prior to entering stop After entering halt mode all background commands are available The interru...

Page 76: ...O reconfigure the peripheral module that interfaces to the pin before writing to PPDACK If the peripheral module is not enabled before writing to PPDACK the pins are controlled by their associated por...

Page 77: ...interrupt from one of the following sources RTC LVD LVW ADC IRQ SCI or KBI 3 9 On Chip Peripheral Modules in Stop and Low Power Modes When the MCU enters any stop mode wait not included system clocks...

Page 78: ...Held SoftNoClk FullNoClk SoftOn FullOn SoftOn Mini FlexBus Pin States Held1 SoftNoClk FullNoClk SoftOn FullOn SoftOn ADC2 3 Off SoftADACK Wakeup FullADACK Wakeup SoftOn FullOn SoftOn FEC Off SoftNoCl...

Page 79: ...transitions through stop2 2 LP mode for the ADC is invoked by setting ADLPC ADACK is selected by the ADCCFG ADICLK field in the ADC See Chapter 15 Analog to Digital Converter ADC12 for details 3 LVD...

Page 80: ...0 to 0x 00 C0 0000 Address Range V1 ColdFire Memory Usage 0x 00 00_0000 Allocated to on chip flash memory 0x 00 3F_FFFF 0x 00 40_0000 Available for off chip expansion 0x 00 7F_FFFF 0x 00 80_0000 Alloc...

Page 81: ...0000 is allocated for on chip RAM Only 24 KB of that is physically implemented on the MCF51CN128 RAM address decoding is aliased every 32 KB across the 2MB region from 0x 00 80_0000 to 0x 00 9F_FFFF R...

Page 82: ...ler x x 0x FF FF_E800 Mini FlexBus x x x x x x Table 4 2 High Level Peripheral Memory Map Peripheral Description Instance Name BaseAddress RGPIO Rapid General Purpose I O RGPIO 0x 00 C0_0000 Port I O...

Page 83: ...sive Approximation Analog to Digital Converter ADC 0x FF FF_8140 SCI Serial Communications Interface SCI1 0x FF FF_8160 SCI Serial Communications Interface SCI2 0x FF FF_8180 SCI Serial Communications...

Page 84: ...ncludes the program visible interrupt controller registers and the space used for interrupt acknowledge IACK cycles There is a nonvolatile register area consisting of a block of 16 bytes in flash memo...

Page 85: ...ADS PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 0x FF FF_800B PTA PTAIFE PTAIFE7 PTAIFE6 PTAIFE5 PTAIFE4 PTAIFE3 PTAIFE2 PTAIFE1 PTAIFE0 Address Peripheral Register Bit 7 6 5 4 3 2 1 Bit 0...

Page 86: ...DS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0 0x FF FF_804B PTE PTEIFE PTEIFE7 PTEIFE6 PTEIFE5 PTEIFE4 PTEIFE3 PTEIFE2 PTEIFE1 PTEIFE0 Address Peripheral Register Bit 7 6 5 4 3 2 1 Bit 0 0x FF...

Page 87: ...FE6 PTHIFE5 PTHIFE4 PTHIFE3 PTHIFE2 PTHIFE1 PTHIFE0 Address Peripheral Register Bit 7 6 5 4 3 2 1 Bit 0 0x FF FF_8080 PTJ PTJD PTJD7 PTJD6 PTJD5 PTJD4 PTJD3 PTJD2 PTJD1 PTJD0 0x FF FF_8081 PTJ PTJDD P...

Page 88: ...KBI1 RTC SPI2 SPI1 0x FF FF_810A SIM SCGC3 PTH PTG PTF PTE PTD PTC PTB PTA 0x FF FF_810B SIM SCGC4 0 0 0 MTIM2 MC MB FEC PTJ 0x FF FF_810C SIM SIMIPS 0 0 0 0 TPM2 TPM1 MTIM2 MTIM1 Address Peripheral R...

Page 89: ...FF_8185 SCI2 SCI2S2 LBKDIF RXEDGI F 0 RXINV RWUID BRK13 LBKDE RAF 0x FF FF_8186 SCI2 SCI2C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0x FF FF_8187 SCI2 SCI2D DATA Address Peripheral Register Bit 7 6 5 4...

Page 90: ...IIC1SLTL SSLT7 SSLT6 SSLT5 SSLT4 SSLT3 SSLT2 SSLT1 SSLT0 0x FF FF_820A IIC1 IC1FLT 0 0 0 0 FLT3 FLT2 FLT1 FLT0 Address Peripheral Register Bit 7 6 5 4 3 2 1 Bit 0 0x FF FF_8220 IIC2 IIC2A1 AD7 AD6 AD5...

Page 91: ...5 14 13 12 11 10 9 Bit 8 0x FF FF_826D TPM1 TPM1C2VL Bit 7 6 5 4 3 2 Bit 1 Bit 0 Address Peripheral Register Bit 7 6 5 4 3 2 1 Bit 0 0x FF FF_8280 TPM2 TPM2SC TOF TOIE CPWMS CLKS PS 0x FF FF_8281 TPM2...

Page 92: ...ASE PROG IFREN NVSTR XE YE SE MAS1 0x FF FF_82E8 0x FF FF_82EF FTSR RESERVED Address Peripheral Register Bit 7 6 5 4 3 2 1 Bit 0 0x FF FF_8300 MTIM2 MTIM2SC TOF TOIE TRST TSTP 0 0 0 0 0x FF FF_8301 MT...

Page 93: ...0 0 TFINT_E N TXB_EN RFINT_E N RXB_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x FF FF_E024 FEC FEC_ECR TAG 0 TEST MD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER_E N RESET 0x FF FF_E...

Page 94: ...DATA R_DATA 31 24 R_DATA 23 16 R_DATA 15 8 R_DATA 7 0 0x FF FF_E090 FEC FEC_AR_DONE AR_HM_B AR_EM_ B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x FF FF_E094 FEC FEC_R_TEST 0 0 0 0 R_...

Page 95: ...E0D0 FEC FEC_X_STATUS 0 0 0 0 0 0 DEF HB LC RL RC UN CSL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x FF FF_E0D4 0x FF FF_E0D7 FEC RESERVED 0x FF FF_E0D8 FEC FEC_X_TEST 0 HBERR BABT GRA X_SPACE _AV X_DONE X_ACC...

Page 96: ...RCONTEXT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z_FLAG 0x FF FF_E108 FEC FEC_D_TEST_CN TRL TEST_MO DE READ_R OM HOLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x FF FF_E10C FEC FEC_D_ACC_RE G...

Page 97: ...FEC_RAND1 RAND1 31 24 RAND1 23 16 RAND1 15 8 RAND1 7 0 0x FF FF_E130 FEC FEC_TMP TMP 31 24 TMP 23 16 TMP 15 8 TMP 7 0 0x FF FF_E140 FEC FEC_FIFO_ID FIFO_REV 0 0 0 0 0 0 0 0 FIFO_SZ 15 8 FIFO_SZ 7 2 0...

Page 98: ...FEC FEC_R_READ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R_READ 9 8 R_READ 7 2 0 0 0x FF FF_E160 FEC FEC_R_WRITE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R_WRITE 9 8 R_WRITE 7 2 0 0 0x FF FF_E16...

Page 99: ...0 0 0 0 0 0 0 0 0 R_BUF_SIZE 6 4 R_BUF_SIZE 3 0 0 0 0 0 0x FF FF_E18C 0x FF FF_E7FF FEC RESERVED Address Peripheral Register Bit 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17...

Page 100: ...F FF_FFCC INTC INTC_ORMR 0 0 0 0 0 0 0 FECDO 0x FF FF_FFCD 0 0 SCI3DO 0 0 0 0 0 Address Peripheral Register Bit 7 6 5 4 3 2 1 Bit 0 0x FF FF_FFD3 INTC INTC_FRC 0 LVL1 LVL2 LVL3 LVL4 LVL5 LVL6 LVL7 0x...

Page 101: ...block protection options Table 4 4 Reserved Flash Memory Addresses Address MSB1 0x0 1 MSB most significant byte 0x1 0x2 LSB2 0x3 2 LSB least significant byte 0x 00 00_03FC Reserved FTRIM bit 0 TRIM 0x...

Page 102: ...flash normally through the background debug interface and verifying the flash is blank 4 3 RAM An MCF51CN128 series microcontroller includes up to 24 KB of static RAM RAM is most efficiently accessed...

Page 103: ...s executing on that specific flash block CAUTION A flash block address must be in the erased state before being programmed Cumulative programming of bits within a flash block address is not allowed ex...

Page 104: ...ister bit are provided in the following sections 4 4 2 1 Flash Clock Divider Register FCDIV The FCDIV register controls the length of timed events in program and erase algorithms executed by the flash...

Page 105: ...ot been written to since the last reset 1 FCDIV register has been written to since the last reset 6 PRDIV8 Enable Prescalar by 8 0 The bus clock is directly fed into the clock divider 1 The bus clock...

Page 106: ...sh protection byte in the flash configuration field indicated by F in Figure 4 7 To change the flash protection loaded during the reset sequence the flash sector containing the flash configuration fie...

Page 107: ...pen 0 Flash array fully protected 1 Flash array protected address range determined by FPS bits Table 4 12 Flash Protection Address Range FPS FPOPEN Protected Address Range Relative to Flash Array Base...

Page 108: ...0000 0x0_FFFF 64 KB 0x60 0x0_0000 0x0_F7FF 62 KB 0x61 0x0_0000 0x0_EFFF 60 KB 0x62 0x0_0000 0x0_E7FF 58 KB 0x63 0x0_0000 0x0_DFFF 56 KB 0x77 0x0_0000 0x0_3FFF 16 KB 0x78 0x0_0000 0x0_37FF 14 KB 0x79 0...

Page 109: ...5 FPVIOL Protection Violation Flag The FPVIOL flag indicates an attempt was made to program or erase an address in a protected area of the flash memory during a command write sequence Writing a 0 to t...

Page 110: ...an choose to allow or disallow a security unlocking mechanism through an 8 byte backdoor security key The security key can be written by the CPU executing from internal memory It cannot be entered wit...

Page 111: ...ead XCSR xcsr 31 24 1000 01 1 xcsr 25 0 Delay TBD cycles A The write IS required 1 1 The last three steps are optional but recommended N number of cycles for SIM to release internal reset Adder of 16...

Page 112: ...t for the ICS Read XCSR xcsr 31 24 1000 01 1 xcsr 25 0 Write PTIMER bits to CSR3 write xcsr 31 24 0x97 to transfer PTIMER info to FTSR and initiate erase verify of flash memory A secure state unknown...

Page 113: ...ster to indicate source of most recent reset Separate interrupt vector for most modules reduces polling overhead see Table 5 1 5 3 Microcontroller Reset Resetting the microcontroller provides a way to...

Page 114: ...ck source and the longest time out 210 cycles When the bus clock source is selected windowed COP operation is available by setting SOPT1 COPW In this mode writes to the SRS register to clear the COP t...

Page 115: ...while levels 1 6 are treated as level sensitive and may be masked depending on the value of the SR I field For correct operation the ColdFire processor requires that once asserted the interrupt sourc...

Page 116: ...rain and is also used during factory test for applying high voltages required for flash test purposes Because of this the RESET PTC3 pin is subject to the following restrictions 1 This pin does not co...

Page 117: ...ided equate file for the MCF51CN128 series microcontrollers The table is sorted by priority of the sources with higher priority sources at the top of the table Note the highlighted entries which do no...

Page 118: ...C1 SPIE SPI2_S MODF SPI2_S SPRF Vspi2 SPI2_C1 SPTIE SPI2_S SPTEF 0x138 5 1 78 MTIM2_ovfl MTIM2_TOF MTIM2_TOIE 0x13C 4 7 79 Next SCI1_err SCI1_C3 ORIE SCI1_S1 OR Vsci1err SCI1_C3 FEIE SCI1_S1 FE SCI1_C...

Page 119: ...EC_EIR BABT 0x170 3 1 92 Next FEC GRA FEC_EIMR GRA FEC_EIR GRA 0x174 2 7 93 Next FEC TXB FEC_EIMR TXB FEC_EIR TXB 0x178 2 6 94 Next FEC RXB FEC_EIMR RXB FEC_EIR RXB 0x17C 2 5 95 Next FEC MII FEC_EIMR...

Page 120: ...112 Next ADC1 ADC_SC1 AIEN ADC_SC1 COCO Vadc 0x1C4 1 2 113 Next KBI1 and KBI2 KBI1_SC KBIE KBI2_SC KBIE KBI1_SC KBF KBI2_SC KBF Vkeyboard 0x1C8 1 1 114 Next RTC RTC_SC RTIE RTC_SC RTIF Vrtc 0x1CC 0x3F...

Page 121: ...r Exception Reset Disabled via CPUCR Reported using SRS 64 108 I O Interrupts N A 61 Unsupported instruction N A 47 Trap 15 N A 46 Trap 14 N A 45 Trap 13 N A 44 Trap 12 N A 43 Trap 11 N A 42 Trap 10 N...

Page 122: ...reset upon detection of a low voltage condition by setting LVDRE The low voltage detection threshold is determined by the LVDV bit After an LVD reset has occurred the LVD system holds the microcontro...

Page 123: ...ng the clocks to the peripheral When clocks are re enabled to a peripheral the peripheral registers need to be re initialized by user software In stop modes the bus clock is disabled for all gated per...

Page 124: ...s reconfigured as an optional pull down device 0 IRQ is falling edge or falling edge low level sensitive 1 IRQ is rising edge or rising edge high level sensitive 4 IRQPE IRQ Pin Enable This read write...

Page 125: ...came from external reset pin 5 COP Computer Operating Properly COP Watchdog Reset was caused by the COP watchdog timer timing out This reset source can be blocked by clearing SOPT1 COPT 0 Reset not ca...

Page 126: ...0 1 1 1 0 0 1 These bits can be written only one time after reset Subsequent writes are ignored Figure 5 3 System Options 1 Register SOPT1 Table 5 6 SOPT1 Field Descriptions Field Description 7 Reserv...

Page 127: ...to the SRS register during the first 75 of the selected period resets the microcontroller 0 Normal mode 1 Window mode Table 5 7 COP Configuration Options Control Bits Clock Source COP Window1 Opens S...

Page 128: ...blocks registers and control bits are located in a target microcontroller Table 5 8 SOPT2 Field Descriptions Field Description 7 RSVD Reserved must be cleared 6 5 FC Flash Configuration These bits sp...

Page 129: ...tings 7 6 5 4 3 2 1 0 R REV1 1 The reset value of 4 bit REV is 0000 for 1 0 Silicon and 0001 for 1 1 Silicon ID11 ID10 ID9 ID8 W Reset 1 1 0 0 Figure 5 6 System Device Identification Register High SDI...

Page 130: ...dge If LVDF is set a low voltage condition has occurred To acknowledge this low voltage detection write 1 to LVDACK which automatically clears LVDF if the low voltage detection is no longer present 5...

Page 131: ...his read only status bit indicates that the voltage regulator has entered into standby for the low power run or wait mode 0 The voltage regulator is not currently in standby 1 The voltage regulator is...

Page 132: ...ing Acknowledge Writing a 1 to LVWACK clears LVWF if a low voltage warning is no longer present 5 LVDV Low Voltage Detect Voltage Select The LVDV bit selects the LVD trip point voltage VLVD 0 Low trip...

Page 133: ...ock Gate Control 0 Bus clock to the MTIM1 module is disabled 1 Bus clock to the MTIM1 module is enabled 6 TPM2 TPM2 Clock Gate Control 0 Bus clock to the TPM2 module is disabled 1 Bus clock to the TPM...

Page 134: ...TSR FTSR Clock Gate Control This bit does not affect normal program execution from the flash array Only the clock to the flash control registers is affected 0 Bus clock to flash registers is disabled...

Page 135: ...1 1 1 Figure 5 13 System Clock Gating Control 3 Register SCGC3 Table 5 18 SCGC3 Register Field Descriptions Field Description 7 PTH PTH Clock Gate Control 0 Bus clock to the PTH module is disabled 1...

Page 136: ...M2 MTIM2 Clock Gate Control 0 Bus clock to the MTIM2 module is disabled 1 Bus clock to the MTIM2 module is enabled 3 MC Port Mux Control 0 Bus clock to the Port Mux Control module is disabled 1 Bus cl...

Page 137: ...plies an external clock signal to the TPM1 module Note that the package pin must also be configured properly using the I O mux controls discussed in Section 9 7 Pin Mux Controls 0 TMRCLK1 1 TMRCLK2 1...

Page 138: ...ontrollable by either an internal or an external reference clock The module can select either of the FLL or PLL clocks or either of the internal or external reference clocks as a source for the MCU sy...

Page 139: ...elected as the clock source for the MCU External reference clock Control for a separate crystal oscillator Clock monitor with reset capability Can be selected as the clock source for the MCU Reference...

Page 140: ...3 2n Internal Reference Clock BDIV MCGLCLK MCGOUT MCGIRCLK EREFS HGO EREFSTEN RANGE IREFSTEN MCGERCLK LP MCGFFCLK DCOOUT PLL VDIV 4 8 12 48 VCO Phase Detector Charge Pump Internal Filter Lock Detector...

Page 141: ...1 Encoding 3 Reserved defaults to 00 5 3 RDIV External Reference Divider Selects the amount to divide down the external reference clock If the FLL is selected the resulting frequency must be in the ra...

Page 142: ...6 2 FLL External Reference Divide Factor RDIV Divide Factor RANGE DIV32 0 X RANGE DIV32 1 0 RANGE DIV32 1 1 0 1 1 32 1 2 2 64 2 4 4 128 3 8 8 256 4 16 16 512 5 32 32 1024 6 64 64 Reserved 7 128 128 Ta...

Page 143: ...w frequency range selected for the crystal oscillator of 32 kHz to 100 kHz 32 kHz to 1 MHz for external clock source 4 HGO High Gain Oscillator Select Controls the crystal oscillator mode of operation...

Page 144: ...eld Descriptions Field Description 7 0 TRIM MCG Trim Setting Controls the internal reference clock frequency by controlling the internal reference clock period The TRIM bits are binary weighted i e bi...

Page 145: ...in FBI and FEI modes RDIV 2 0 bits in FBE FEE PBE and PEE modes VDIV 3 0 bits in PBE and PEE modes and PLLS bit causes the lock status bit to clear and stay clear until the FLL or PLL has reacquired l...

Page 146: ...if an interrupt request is made following a loss of lock indication The LOLIE bit only has an effect when LOLS is set 0 No request on loss of lock 1 Generate an interrupt request on loss of lock 6 PLL...

Page 147: ...he multiplication factor M applied to the reference clock frequency 0000 Encoding 0 Reserved 0001 Encoding 1 Multiply by 4 0010 Encoding 2 Multiply by 8 0011 Encoding 3 Multiply by 12 0100 Encoding 4...

Page 148: ...te 1 s to these bits 1 0 DRST DRS DCO Range Status The DRST read bits indicate the current frequency range for the FLL output DCOOUT See Table 6 9 The DRST bits do not update immediately after a write...

Page 149: ...to 1024 times the internal reference frequency MCGLCLK is derived from the FLL and the PLL is disabled in a low power state FLL Bypassed External FBE MCGC1 IREFS 0 MCGC1 CLKS 10 MCGC1 RDIV is program...

Page 150: ...sabled in a low power state Bypassed Low Power Internal BLPI MCGC1 IREFS 1 MCGC1 CLKS 01 MCGC2 LP 1 and the BDM is disabled MCGOUT is derived from the internal reference clock The PLL and FLL are disa...

Page 151: ...available the previous clock remains selected The DRS bits can be changed at anytime except when LP bit is 1 If the DRS bits are changed while in FLL engaged internal FEI or FLL engaged external FEE...

Page 152: ...y POR but is not affected by other resets If IREFSTEN and IRCLKEN bits are set the internal reference clock keeps running during stop mode to provide a fast recovery upon exiting stop All MCU devices...

Page 153: ...n acquire lock As soon as the internal reference is stable the FLL acquires lock in tfll_acquire milliseconds NOTE If the internal reference is not already trimmed the BDIV value should not be changed...

Page 154: ...ng bus clock frequency does not exceed the maximum specified bus clock frequency of the device By default with DMX32 cleared to 0 the FLL multiplier for the DCO output is 512 For greater flexibility i...

Page 155: ...maximum DCO output of 39 85 MHz with a multiplier of 1216 When the DRS 1 0 bits are set to 10 the 32 768 kHz reference can achieve a high range maximum DCO output of 59 77 MHz with a multiplier of 182...

Page 156: ...o achieve a bus frequency of 16 MHz Because the MCG is in FEI mode out of reset this example also shows how to initialize the MCG for PEE mode out of reset First the code sequence is described Then a...

Page 157: ...set to 1 selects the PLL At this time with an RDIV value of 011 the FLL reference divider of 256 is switched to the PLL reference divider of 8 see Table 6 3 resulting in a reference frequency of 8 MH...

Page 158: ...or MCG MCF51CN128 Reference Manual Rev 6 Freescale Semiconductor 6 21 b Now With an RDIV of divide by 8 a BDIV of divide by 1 and a VDIV of multiply by 32 MCGOUT 8 MHz 8 32 1 32 MHz and the bus freque...

Page 159: ...ition using an 8 MHz crystal MCGC2 0x36 CHECK OSCINIT 1 CHECK IREFST 0 CHECK CLKST 10 ENTER BLPE MODE MCGC2 0x3E LP 1 MCGC3 0x58 IN BLPE MODE LP 1 MCGC2 0x36 LP 0 CHECK PLLST 1 MCGC1 0x18 CHECK LOCK 1...

Page 160: ...11 necessary to achieve required 31 25 39 06 kHz FLL reference frequency with an 8 MHz external source frequency it must be changed prior to clearing the PLLS bit In BLPE mode changing this bit only p...

Page 161: ...Rev 6 6 24 Freescale Semiconductor 4 Lastly FBI transitions into BLPI mode a MCGC2 0x08 00001000 LP bit 3 in MCGSC is 1 RANGE HGO EREFS ERCLKEN and EREFSTEN bits are ignored when the IREFS bit bit2 in...

Page 162: ...o BLPI Mode Transition using an 8 MHz crystal MCGC1 0x98 CHECK CLKST 10 MCGC2 0x3E MCGC1 0x5C CHECK IREFST 0 CHECK CLKST 01 CONTINUE IN BLPI MODE START IN PEE MODE MCGC3 0x18 ENTER BLPE MODE IN BLPE M...

Page 163: ...l OSCINIT bit 1 in MCGSC is 1 indicating the crystal selected by the EREFS bit has been initialized c MCGC1 0x18 00011000 CLKS bits 7 and 6 set to 00 to select the output of the FLL as system clock so...

Page 164: ...it is the LSB The trim value after reset is the factory trim value unless the device resets into any BDM mode in which case it is 0x800 Writing a larger value decreases the frequency and smaller value...

Page 165: ...opying the saved value from flash to the MCG registers Freescale identifies recommended flash locations for storing the trim value for each MCU Consult the memory map in the data sheet for these locat...

Page 166: ...ecommended to trim using a reference divider value RDIV setting of twice the final value After the trim procedure is complete the reference divider can be restored This prevents accidental overshoot o...

Page 167: ...ores the V1 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer Figure 7 1 V1 ColdFire Core Pipelines The instruction fetch pipeline IFP is a two stage pipeline for...

Page 168: ...e V1 core contains three longwords of storage For register to register and register to memory store operations the instruction passes through both OEP stages once For memory to register and read modif...

Page 169: ...2 7 4 Load 0x6F Store 0x4F User A7 Stack Pointer A7 32 R W POR Undefined Else Unaffected No 7 2 3 7 4 Load 0xEE Store 0xCE Condition Code Register CCR 8 R W POR Undefined Else Unaffected No 7 2 4 7 5...

Page 170: ...HER_A7 Thus the register contents are a function of the processor operation mode as shown in the following if SR S 1 then A7 Supervisor Stack Pointer OTHER_A7 User Stack Pointer else A7 User Stack Poi...

Page 171: ...y processor operations The extend bit X is also an input operand during multiprecision arithmetic computations The CCR register must be explicitly loaded after reset and before any compare CMP Bcc or...

Page 172: ...e bit Set if most significant bit of the result is set otherwise cleared 2 Z Zero condition code bit Set if result equals zero otherwise cleared 1 V Overflow condition code bit Set if an arithmetic ov...

Page 173: ...a reset event 1 No reset is generated in response to these exception conditions 30 IRD Instruction related reset disable Used to disable the generation of a reset event in response to a processor exce...

Page 174: ...fered writes are enabled BWD 0 any error status is lost as the immediate termination of the data transfer assumes an error free completion 26 Reserved must be cleared 25 FSD Flash speculation disabled...

Page 175: ...word sized operands Full support for the move byte and move word instructions was provided but the only other opcodes supporting these data types are CLR clear and TST test A set of instruction enhanc...

Page 176: ...gnificant bit Dn 31 and ending with the least significant bit Dn 0 searching for the first set bit The data register is then loaded with the offset count from bit 31 where the first set bit appears MO...

Page 177: ...rmine the address of the first instruction of the desired handler After the instruction fetch for the first opcode of the handler has initiated exception processing terminates and normal instruction p...

Page 178: ...al 7 3 2 1 Exception Stack Frame Definition Figure 7 10 shows exception stack frame The first longword contains the 16 bit format vector word F V and the 16 bit status register and the second longword...

Page 179: ...the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt See Table 7 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 180: ...occurs contain the operands from memory The V1 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes Because the actual write cycle may be decoupled from the pro...

Page 181: ...egment the entire ISA into 16 instruction lines the next 6 bits define the operation mode opmode and the low order 6 bits define the effective address See Figure 7 11 The opword line definition is sho...

Page 182: ...1 ColdFire processor is the generation of an illegal opcode reset event if a privilege violation is detected If CPUCR IRD is set the reset is disabled and a processor exception is generated as detaile...

Page 183: ...0b1010 This exception is generated by the attempted execution of an undefined line A opcode 7 3 3 7 Unimplemented Line F Opcode The default operation of the V1 ColdFire processor is the generation of...

Page 184: ...processing of the software scheduled IRQs can be masked based on the interrupt priority level defined by the SR I field 7 3 3 11 Unsupported Instruction Exception If execution of a valid instruction i...

Page 185: ...r is granted the bus it performs two longword read bus cycles The first longword at address 0x 00 00_0000 is loaded into the supervisor stack pointer and the second longword at address 0x 00 00_0004 i...

Page 186: ...is present in processor core 0 MAC execute engine not present in core This is the value used for this device 1 MAC execute engine is present in core 14 DIV Divide present This bit signals if the hard...

Page 187: ...on memory size The size shown is for 128 KB flash Figure 7 13 D1 Hardware Configuration Info Table 7 11 D1 Hardware Configuration Information Field Description Field Description 31 24 Reserved 18 16 R...

Page 188: ...on example of stall involves consecutive store operations excluding the MOVEM instruction For all STORE operations except MOVEM certain hardware resources within the processor are marked as busy for t...

Page 189: ...Ax d8 Ax Xi SF xxx wl Dy 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 Ay 2 1 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 Ay 2 1 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1...

Page 190: ...ITREV Dx 1 0 0 BYTEREV Dx 1 0 0 CLR B ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 CLR W ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 CLR L ea 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 EXT W Dx 1 0 0...

Page 191: ...4 1 1 5 1 1 4 1 1 BCHG imm ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 BCLR Dy ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1 1 4 1 1 BCLR imm ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 BSET Dy ea 2 0 0 4 1 1 4 1 1 4 1 1 4 1 1 5 1...

Page 192: ...a 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 MOVE L Ay USP 3 0 0 MOVE L USP Ax 3 0 0 MOVE W CCR Dx 1 0 0 MOVE W ea CCR 1 0 0 1 0 0 MOVE W SR Dx 1 0 0 MOVE W ea SR 7 0 0 7 0 0 2 MOVEC Ry Rc 9 0 1 MOVEM...

Page 193: ...sly for interrupts 4 PEA execution times are the same for d16 PC 5 PEA execution times are the same for d8 PC Xn SF Table 7 18 General Branch Instruction Execution Times Opcode EA Effective Address Rn...

Page 194: ...h a minimal hardware implementation and cost Table 8 1 provides a high level architectural comparison between HCS08 and ColdFire exception processing as these differences are important in the definiti...

Page 195: ...ns from detecting the fault condition to the initiation of fetch for the first handler instruction Exception processing is comprised of four major steps 1 The processor makes an internal copy of the s...

Page 196: ...ssors support a 1024 byte vector table aligned on any 1 MB address boundary For the V1 ColdFire core the only practical locations for the vector table are based at 0x 00 00_0000 in the flash or 0x 00...

Page 197: ...0x130 5 3 76 Next SPI1 SPI1_C1 SPIE SPI1_S MODF SPI1_S SPRF Vspi1 SPI1_C1 SPTIE SPI1_S SPTEF 0x134 5 2 77 Next SPI2 SPI2_C1 SPIE SPI2_S MODF SPI2_S SPRF Vspi2 SPI2_C1 SPTIE SPI2_S SPTEF 0x138 5 1 78...

Page 198: ...BERR FEC_EIMR HBERR FEC_EIR HBERR 0x168 3 3 90 Next FEC BABR FEC_EIMR BABR FEC_EIR BABR 0x16C 3 2 91 Next FEC BABT FEC_EIMR BABT FEC_EIR BABT 0x170 3 1 92 Next FEC GRA FEC_EIMR GRA FEC_EIR GRA 0x174 2...

Page 199: ...KBI2 KBI1_SC KBIE KBI2_SC KBIE KBI1_SC KBF KBI2_SC KBF Vkeyboard 0x1C8 1 1 114 Next RTC RTC_SC RTIE RTC_SC RTIF Vrtc 0x1CC 0x3FC N A N A 115 255 Next Reserved 1 The SCI3_OR interrupt is a logical ORin...

Page 200: ...able for I O interrupt requests The requirement for an exact match between the interrupt requests and priorities across two architectures means the sources are mapped to a sparsely populated two dimen...

Page 201: ...el and vector sent directly to processor core Support of 44 peripheral I O interrupt requests plus seven software one per level interrupt requests Fixed association between interrupt request source an...

Page 202: ...toring the assertion of an interrupt request After a request of unmasked level is asserted this combinational logic path asserts an output signal that is sent to the clock generation logic to re enabl...

Page 203: ...40 8 3 1 8 10 0x10 INTC_FRC CF1_INTC Force Interrupt Register 8 R W 0x00 8 3 2 8 11 0x18 INTC_PL6P7 CF1_INTC Programmable Level 6 Priority 7 8 R W 0x00 8 3 3 8 12 0x19 INTC_PL6P6 CF1_INTC Programmable...

Page 204: ..._SFRC INTC_CFRC NOTE Take special notice of the bit numbers within this register 63 56 This is for compatibility with other ColdFire interrupt controllers Offset CF1_INTC_BASE 0x0C INTC_ORMR Access Re...

Page 205: ...gure 8 3 Force Interrupt Register INTC_FRC Table 8 6 INTC_FRC Field Descriptions Field Description 63 Reserved must be cleared 62 LVL1 Force Level 1 interrupt 0 Negates the forced level 1 interrupt re...

Page 206: ...ait mode INTC_WCR MASK The maximum value of INTC_WCR MASK is 0x6 0b110 The INTC_WCR is enabled with a mask level of 0 as the default after reset 2 Execute a stop instruction to place the processor int...

Page 207: ...o interrupt service routines can generate a forced interrupt request without the need to perform a read modify write sequence on the INTC_FRC register Figure 8 6 INTC_SFRC Register Offset CF1_INTC_BAS...

Page 208: ...L6 is set 0x3A Bit 58 INTC_FRC LVL5 is set 0x3B Bit 59 INTC_FRC LVL4 is set 0x3C Bit 60 INTC_FRC LVL3 is set 0x3D Bit 61 INTC_FRC LVL2 is set 0x3E Bit 62 INTC_FRC LVL1 is set Note Data values outside...

Page 209: ...This means the interrupt source must be explicitly disabled in the peripheral device by the interrupt service routine This approach provides unique vector capability for all interrupt requests regard...

Page 210: ...fter reset the CF1_INTC begins its cycle by cycle evaluation of any asserted interrupt requests and forms the appropriate encoded interrupt level and vector information for the V1 Coldfire processor c...

Page 211: ...the ColdFire implementation enables interrupts by clearing SR I typically when using RTE to return to a process and disables interrupts upon entering every interrupt service routine by one of three me...

Page 212: ...on prologue to allocate space on the supervisor stack to save the four volatile registers d0 d1 a0 a1 defined in the ColdFire application binary interface After saving these registers the ISR continue...

Page 213: ...able is based at address 0x 00 00_0000 and that each ISR uses the same two instruction prologue shown here The resulting alternate entry point is a fixed offset 8 bytes from the normal entry point def...

Page 214: ...lity similar to standard GPIO with the addition of set clear toggle functionality but at CPU rather than peripheral bus clock rates Table 9 1 Functionality on a Per Port Basis Port Name Width GPIO Imp...

Page 215: ...y select which function owns a pin with the port mux control MC registers These are defined in detail in Section 9 7 9 1 5 Special Cases 9 1 5 1 Pull Up Resistors After reset the shared peripheral fun...

Page 216: ...xPE n 0 Two exceptions to this are the RESET and BKGD MS pins which have pull ups enabled at reset 9 1 5 2 Port J Port J has only 6 pins versus the usual 8 associated with it Always write the upper tw...

Page 217: ...rive strength and input filter enables for the pins They may also be used in conjunction with the peripheral functions on these pins These registers are associated with the parallel I O ports and Rapi...

Page 218: ...red as an output by the parallel I O control logic Configured as a shared peripheral function Controlled by an analog function At reset except for RESETB and BKGD MS Table 9 6 Register Set Summary Reg...

Page 219: ...bled pin into a smaller load Because of this the EMC emissions may be affected by enabling pins as high drive 7 6 5 4 3 2 1 0 R PTxSE7 PTxSE6 PTxSE5 PTxSE4 PTxSE3 PTxSE2 PTxSE1 PTxSE0 W Reset 0 0 0 0...

Page 220: ...or port data register reads The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output only pin When a shared digital function is enabled...

Page 221: ...n GPIO signals to the MCF51CN128 package pins Most pin functions default to GPIO and must be software configured 9 3 2 GPIO Programming Model Refer to tables in Chapter 4 Memory for the absolute addre...

Page 222: ...0 0 0 Figure 9 7 Port x Data Register PTxD Table 9 12 PTxD Field Descriptions Field Description 7 0 PTxDn Port x Data Register Bits For Port x pins that are inputs reads return the logic level on the...

Page 223: ...sitivity can be software programmed to be falling or rising the level can be either low or high The polarity of the edge sensitivity or edge and level sensitivity is selected using the KBIxES KBEDGn S...

Page 224: ...it is possible to get a false interrupt flag To prevent a false interrupt request during pin interrupt initialization do the following 1 Mask interrupts by clearing KBIxSC KBIE 2 Select the pin polari...

Page 225: ...cknowledge Writing a 1 to KBACK is part of the flag clearing mechanism KBACK always reads as 0 1 KBIE KBIx Interrupt Enable KBIE determines whether a KBIx interrupt is requested 0 KBIx interrupt reque...

Page 226: ...s set I O register states should be restored from the values saved in RAM before the STOP instruction was executed and peripherals may require initialization or restoration to their pre stop condition...

Page 227: ...registers that configure monitor and control the port pins NOTE Use pin mux control registers from Section 2 3 Pin Mux Controls to assign RGPIO signals to the MCF51CN128 package pins Most pin function...

Page 228: ...e processor s local bus All memory references complete in a single cycle to provide zero wait state responses Located in processor s high speed clock domain Simple programming model Four 16 bit regist...

Page 229: ...ons Table 10 2 provides descriptions of the RGPIO module s input and output signals Table 10 1 RGPIO Module External I O Signals Signal Name Type Description RGPIO 15 0 I O RGPIO Data Input Output Tab...

Page 230: ...Map Offset Address Register Width bits Access Reset Value Section Page 0x00 RGPIO Data Direction Register RGPIO_DIR 16 W 0x0000 10 3 1 10 5 0x02 RGPIO Write Data Register RGPIO_DATA 16 W 0x0000 10 3 2...

Page 231: ...r disabled pins since the data value is dependent on the device level pin muxing and pad implementation The RGPIO_DATA register is read write At reset all bits in the RGPIO_DATA registers are cleared...

Page 232: ...O_DATA RGPIO_Base 0x6 RGPIO_Base 0xA RGPIO_Base 0xE Access Read write Read Indirect Write Read Indirect Write Read Indirect Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 0...

Page 233: ...oggle Data RGPIO_TOG The RGPIO_TOG register provides a mechanism to invert toggle specific bits in the RGPIO_DATA register by performing a simple write Setting a bit in RGPIO_TOG inverts the correspon...

Page 234: ...ort Prior to using the RGPIO port software typically Enables the appropriate pins in RGPIO_ENB Configures the pin direction in RGPIO_DIR Defines the contents of the data register RGPIO_DATA 10 6 Appli...

Page 235: ...propriate number of square wave pulse have been generated The square wave output frequency was measured and the relative performance results are presented in Table 10 11 The relative performance is st...

Page 236: ...s 0052e 3140 fffd mov w d0 3 a0 set RGPIO_DIR register 00532 3140 0001 mov w d0 1 a0 set RGPIO_ENB register 00536 223c 0001 0000 mov l 0x10000 d1 d1 17 16 clk cs 0053c 2001 mov l d1 d0 copy into temp...

Page 237: ...10 11 MCF51CN128 Reference Manual Rev 6 Table 10 12 Emulated SPI Performance using GPIO Outputs Peripheral Bus mapped GPIO RGPIO SPI Speed CPU f 50 MHz Relative Speed SPI Speed CPU f 50 MHz Relative...

Page 238: ...fsys Use pin mux control registers from Section 2 3 Pin Mux Controls to assign Mini FlexBus signals to the MCF51CN128 package pins Most pin functions default to GPIO and must be software configured be...

Page 239: ...erations 11 2 1 Address and Data Buses FB_A 19 0 FB_D 7 0 FB_AD 0 In non multiplexed mode the FB_A 19 0 and FB_D 7 0 buses carry the address and data respectively Up to a 20 bit address non multiplexe...

Page 240: ...r FB_OE is only asserted during read accesses when a chip select matches the current address decode 11 2 4 Read Write FB_R W The processor drives the FB_R W signal to indicate the current bus operatio...

Page 241: ...00 11 3 2 11 4 0x08 0x14 Chip Select Control Register CSCRn n 0 1 32 R W See Section 11 3 3 11 5 Address 0x00 CSAR0 0x0C CSAR1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 242: ...equals 0x0040 CSMR0 BAM equals 0x001F CSAR1 equals 0x0060 and CSMR1 BAM equals 0x000F 15 9 Reserved must be cleared 8 WP Write protect Controls write accesses to the address range in the corresponding...

Page 243: ...y at the end of a transfer Therefore during a transfer to a port size smaller than the transfer size the hold time is only added after the last bus cycle 00 Hold address and attributes one cycle after...

Page 244: ...sizing is programmable through the port size bits CSCR PS The processor always drives a 20 bit address on the FB_AD bus regardless of the external device s address size The external device must 7 6 PS...

Page 245: ...s Transfer parameters address setup and hold port size the number of wait states for the external device being accessed automatic internal transfer termination enable or disable are programmed in the...

Page 246: ...utes and FB_ALE are driven 2 S1 FB_CSn is asserted at the second rising clock edge to indicate the device selected by that time the address and attributes are valid and stable FB_ALE is negated at thi...

Page 247: ...the device places a valid address on FB_AD 19 0 asserts FB_ALE and drives FB_R W high for a read and low for a write S1 All FB_ALE is negated on the rising edge of FB_CLK and FB_CSn is asserted Data...

Page 248: ...uring the first clock cycle of the transfer with the full 20 bit address This may be ignored by standard connected devices using non multiplexed address and data buses However some applications may fi...

Page 249: ...e Cycle Flowchart FB_CLK FB_R W S0 S1 S2 S3 FB_ALE Mux d Bus Non Mux d Bus FB_A 19 0 FB_D 7 0 FB_AD X 0 FB_CSn FB_OE DATA DATA ADDR 19 0 ADDR X 0 ADDR 19 X 1 S0 FB_AD 19 X 1 1 Select the appropriate s...

Page 250: ...e Sizing This section shows timing diagrams for various port size scenarios Figure 11 10 illustrates the basic byte read transfer to an 8 bit device with no wait states The address is driven on the fu...

Page 251: ...sfer Figure 11 11 shows the similar configuration for a write transfer The data is driven from the second clock on FB_AD 7 0 Figure 11 11 Single Byte Write Transfer 7 0 19 8 FB_CLK S0 S1 S2 S3 FB_R W...

Page 252: ...the bus cycle The external device returns the read data on FB_AD 15 0 NOTE In non multiplexed mode the Mini FlexBus does not support connection to a 16 bit device Figure 11 12 Single Word Read Transfe...

Page 253: ...ad or write bus cycle to provide additional address setup address hold and time for a device to provide or latch data 11 4 6 4 1 Wait States Wait states can be inserted before each beat of a transfer...

Page 254: ...states Figure 11 14 Basic Read Bus Cycle No Wait States Figure 11 15 Basic Write Bus Cycle No Wait States FB_CLK FB_R W FB_ALE S0 S1 S2 S3 DATA DATA Mux d Bus Non Mux d Bus FB_A 19 0 ADDR 19 0 FB_D 7...

Page 255: ...w a read and write cycle with one wait state Figure 11 16 Read Bus Cycle One Wait State Figure 11 17 Write Bus Cycle One Wait State FB_CLK FB_R W FB_ALE S0 S1 WS S2 S3 DATA DATA Mux d Bus Non Mux d Bu...

Page 256: ...igure 11 18 and Figure 11 19 show read and write bus cycles with two clocks of address setup Figure 11 18 Read Bus Cycle with Two Clock Address Setup No Wait States Figure 11 19 Write Bus Cycle with T...

Page 257: ...how read and write bus cycles with two clocks of address hold Figure 11 20 Read Cycle with Two Clock Address Hold No Wait States Figure 11 21 Write Cycle with Two Clock Address Hold No Wait States FB_...

Page 258: ...e disabled using the platform peripheral power management control Mini FlexBus accesses cause an error termination on the bus and prohibit the access to the Mini FlexBus Attempted writes to space defi...

Page 259: ...periodic interrupt This module can be used for time of day calendar or any task scheduling functions It can also serve as a cyclic wakeup from low power modes without the need of external components N...

Page 260: ...pt is enabled For lowest possible current consumption the RTC should be stopped by software if not needed as an interrupt source during wait mode 12 1 2 2 Stop Modes The RTC continues to run in stop2...

Page 261: ...egister Refer to the direct page register summary in Chapter 4 Memory for the absolute address assignments for all RTC registers This section refers to registers and control bits only by their names a...

Page 262: ...rescaler Changing the clock source clears the prescaler and RTCCNT counters When selecting a clock source ensure that the clock source is properly enabled if applicable to ensure correct operation of...

Page 263: ...he external clock ERCLK and the internal clock IRCLK The RTC clock select bits RTCLKS select the desired clock source If a different value is written to RTCLKS the prescaler and RTCCNT counters are re...

Page 264: ...an interrupt to be generated when RTIF is set To enable the real time interrupt set the real time interrupt enable bit RTIE in RTCSC RTIF is cleared by writing a 1 to RTIF 12 4 1 RTC Operation Exampl...

Page 265: ...ze and configure the RTC module The example software is implemented in C language The example below shows how to implement time of day with the RTC using the 1 kHz clock source to achieve the lowest p...

Page 266: ...Rev 6 Freescale Semiconductor 12 8 RTCSC byte RTCSC byte 0x80 RTC interrupts every 1 Second Seconds 60 seconds in a minute if Seconds 59 Minutes Seconds 0 60 minutes in an hour if Minutes 59 Hours Min...

Page 267: ...not include stop1 low power mode Ignore references to stop1 in this chapter For details on low power mode operation refer to Table 3 5 in Chapter 3 Modes of Operation Use pin mux control registers fr...

Page 268: ...nual Rev 6 13 2 Freescale Semiconductor Figure 13 1 SCI Module Block Diagram BAUDRATE GENERATOR RECEIVER TRANSMITTER ipp_ind_sci_rx SBR12 SBR0 MODULE CLOCK 16 ipp_ind_sci_tx LOOP CONTROL SINGLE WIRE i...

Page 269: ...Receive data register full Receive overrun parity error framing error and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checki...

Page 270: ...m H 8 7 6 5 4 3 2 1 0 L SCID Tx Buffer Write Only Internal Bus Stop 11 BIT Transmit Shift Register Start SHIFT DIRECTION lsb 1 Baud Rate Clock Parity Generation Transmit Control Shift Enable Preamble...

Page 271: ...r Read only Internal Bus Stop 11 Bit Receive Shift Register Start Shift Direction lsb From RxD Pin Rate Clock Rx Interrupt Request Data Recovery Divide 16 Baud Single Wire Loop Control Wakeup Logic Al...

Page 272: ...non zero value so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled RE or TE bits in SCIxC2 are written to 1 7 6 5 4 3 2 1 0 R LBKDIE RX...

Page 273: ...ISWAI SCI Stops in Wait Mode 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU 1 SCI clocks freeze while CPU is in wait mode 5 RSRC Receiver...

Page 274: ...cluding the parity bit is even 0 Even parity 1 Odd parity 7 6 5 4 3 2 1 0 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0 0 0 0 0 0 Figure 13 7 SCI Control Register 2 SCIxC2 Table 13 4 SCIxC2 Field De...

Page 275: ...eral purpose I O pin even if RE is set 0 Receiver off 1 Receiver on 1 RWU Receiver Wakeup Control This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic...

Page 276: ...racter is all 1s these bit times and the stop bit time count toward the full character time of logic high 10 or 11 bit times depending on the M control bit needed for the receiver to detect an idle li...

Page 277: ...try is enabled and a LIN break character is detected LBKDIF is cleared by writing a 1 to it 0 No LIN break character has been detected 1 LIN break character has been detected 6 RXEDGIF RxD Pin Active...

Page 278: ...a start bit 1 SCI receiver active RxD input not idle 1 Setting RXINV inverts the RxD input for all cases data bits start and stop bits break and idle 7 6 5 4 3 2 1 0 R R8 T8 TXDIR TXINV ORIE NEIE FEI...

Page 279: ...TXINV1 Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable This bit enab...

Page 280: ...transmitter output TxD idle state defaults to logic high TXINV is cleared following reset The transmitter output is inverted by setting TXINV The transmitter is enabled by setting the TE bit in SCIxC2...

Page 281: ...rite 1 to the TE bit This action queues an idle character to be sent as soon as the shifter is available As long as the character in the shifter does not finish while TE is cleared the SCI transmitter...

Page 282: ...e start bit the bit is assumed to be 0 if at least two of the samples at RT3 RT5 and RT7 are 0 even if one or all of the samples taken at RT8 RT9 and RT10 are 1s If any sample in any bit time includin...

Page 283: ...cally when the receiver detects a logic 1 in the most significant bit of a received character eighth bit when M is cleared and ninth bit when M is set Address mark wakeup allows messages to contain id...

Page 284: ...eady set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun OR flag is set instead of the data along with any associated NF FE or PF condit...

Page 285: ...d to check software independent of connections in the external system to help isolate system problems In this mode the transmitter output is internally connected to the receiver input and the RxD pin...

Page 286: ...shift registers sensors memories etc The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock divided by 4 in slave mode Software can poll the status flags...

Page 287: ...tem Block Diagram Figure 14 1 shows the SPI modules of two MCUs connected in a master slave arrangement The master device initiates all SPI data transfers During a transfer the master shifts data out...

Page 288: ...to the double buffered transmitter write to SPIxD and gets transferred to the SPI shift register at the start of a data transfer After shifting in a byte of data the data is transferred into the doub...

Page 289: ...SPR2 SPR1 SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 or 256 to get the internal SPI master mode bit rate clock SPI Shift Register Shift Clock Shift Direction Rx Buffer Full T...

Page 290: ...ed this pin is not used by the SPI and reverts to being a general purpose port I O pin 14 2 3 MISO Master Data In Slave Data Out When the SPI is enabled as a master and SPI pin control zero SPC0 is 0...

Page 291: ...nly by their names and a Freescale provided equate or header file is used to translate these names into the appropriate absolute addresses 14 4 1 SPI Control Register 1 SPIxC1 This read write register...

Page 292: ...kinds of synchronous serial peripheral devices Refer to Section 14 5 1 SPI Clock Formats for more details 0 First edge on SPSCK occurs at the middle of the first cycle of an 8 cycle data transfer 1 Fi...

Page 293: ...an input 1 SPI I O pin enabled as an output 1 SPISWAI SPI Stop in Wait Mode 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode 0 SPC0 SPI Pin Control 0 The...

Page 294: ...es have no meaning or effect Table 14 5 SPI Baud Rate Prescaler Divisor SPPR2 SPPR1 SPPR0 Prescaler Divisor 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Table 14 6 SPI Baud Rate Div...

Page 295: ...data value to the transmit buffer at SPIxD SPIxS must be read with SPTEF set before writing data to SPIxD or the SPIxD write is ignored SPTEF generates an SPTEF CPU interrupt request if the SPTIE bit...

Page 296: ...etails Because the transmitter and receiver are double buffered a second byte in addition to the byte currently being shifted out can be queued into the transmit data buffer and a previously received...

Page 297: ...slave The next SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs respectively At the third SPSCK edge the SPI shifter shifts one bit position...

Page 298: ...HA 0 the slave begins to drive its MISO output with the first data bit value MSB or LSB depending on LSBFE when SS goes to active low The first SPSCK edge causes both the master and the slave to sampl...

Page 299: ...e SS pin is configured as the mode fault input signal The SS pin is configured to be the mode fault input signal when MSTR is set mode fault enable is set MODFEN 1 and slave select output enable is cl...

Page 300: ...s from Section 2 3 Pin Mux Controls to assign ADC signals to the MCF51CN128 package pins Most pin functions default to GPIO and must be software configured before using ADC 15 1 1 ADC Clock Gating The...

Page 301: ...000 AD0 PTE2 KBI2P2 SS2 ADP0 10000 AD16 Reserved 00001 AD1 PTE1 KBI2P1 MOSI2 ADP1 10001 AD17 Reserved 00010 AD2 PTE0 KBI2P0 MISO2 ADP2 10010 AD18 Reserved 00011 AD3 PTD7RGPIO7 SPSCK2 ADP3 10011 AD19 R...

Page 302: ...cause a hardware trigger in MCU run wait and stop3 15 1 2 4 Temperature Sensor The ADC module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs Equation 1...

Page 303: ...version automatic return to idle after single conversion Configurable sample time and conversion speed power Conversion complete flag and interrupt Input clock selectable from up to four sources Opera...

Page 304: ...27 AD0 Analog Channel inputs VREFH High reference voltage VREFL Low reference voltage VDDAD Analog power supply VSSAD Analog ground AD0 AD27 VREFH VREFL ADVIN ADCH Control Sequencer initialize sample...

Page 305: ...ay be driven by an external source between the minimum VDDAD spec and the VDDAD potential VREFH must never exceed VDDAD 15 2 4 Voltage Reference Low VREFL VREFL is the low reference voltage for the co...

Page 306: ...when software triggered operation is selected or one conversion following assertion of ADHWT when hardware triggered operation is selected 1 Continuous conversions initiated following a write to ADCSC...

Page 307: ...0 R1 W Reset 0 0 0 0 0 0 0 0 Figure 15 3 Status and Control Register 2 ADCSC2 Table 15 5 ADCSC2 Register Field Descriptions Field Description 7 ADACT Conversion Active Indicates that a conversion is...

Page 308: ...ntil the after next conversion is completed the intermediate conversion results are lost In 8 bit mode there is no interlocking with ADCRH If the MODE bits are changed any data in ADCRL becomes invali...

Page 309: ...re Value Low Register ADCCVL 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset 0 0 0 0 0 0 0 0 Figure 15 8 Configuration Register ADCCFG Table 15 6 ADCCFG Register Field Descriptions Field Descr...

Page 310: ...tage is converted by a successive approximation algorithm into a 9 bit digital result 3 2 MODE Conversion Mode Selection MODE bits are used to select between 12 10 or 8 bit operation See Table 15 8 1...

Page 311: ...a clock source within the ADC module When selected as the clock source this clock remains active while the MCU is in wait or stop3 mode and allows conversions in these modes for lower noise operation...

Page 312: ...egin after a hardware trigger event and continue until aborted 15 4 4 2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers...

Page 313: ...ample times When sampling is complete the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal The res...

Page 314: ...COCO is set The value generated by the addition of the conversion result and the two s complement of the compare value is transferred to ADCRH and ADCRL Upon completion of a conversion while the compa...

Page 315: ...the ADC in its idle state The contents of ADCRH and ADCRL are unaffected by stop3 mode After exiting from stop3 mode a software or hardware trigger is required to resume conversions 15 4 7 2 Stop3 Mo...

Page 316: ...ical sequence is as follows 1 Update the configuration register ADCCFG to select the input clock source and the divide ratio used to generate the internal clock ADCK This register is also used for sel...

Page 317: ...ompletes Bit 6 AIEN 1 Conversion complete interrupt enabled Bit 5 ADCO 0 One conversion only continuous conversions disabled Bit 4 0 ADCH 00001 Input channel 1 selected as ADC input channel ADCRH L 0x...

Page 318: ...d connection between these supplies must be at the VSSAD pin This should be the only ground connection between these supplies if possible The VSSAD pin makes a good single point ground location 15 6 1...

Page 319: ...full scale 10 bit representation or 0xFF full scale 8 bit representation If the input is equal to or less than VREFL the converter circuit converts it to 0x000 Input voltages between VREFH and VREFL a...

Page 320: ...be placed in wait or stop3 or I O activity cannot be halted these recommended actions may reduce the effect of noise on the accuracy Place a 0 01 F capacitor CAS on the selected input channel to VREF...

Page 321: ...e the absolute value of the running sum of DNL achieves More simply this is the worst case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage fo...

Page 322: ...128 package pins Most pin functions default to GPIO and must be software configured before using FEC 16 1 1 Overview The Ethernet media access controller MAC supports 10 and 100 Mbps Ethernet IEEE 802...

Page 323: ...ve frames Random number generation for transmit collision backoff timer The RAM is the focal point of all data flow in the Fast Ethernet controller and divides into transmit and receive FIFOs The FIFO...

Page 324: ...wing features Support for three different Ethernet physical interfaces 100 Mbps IEEE 802 3 MII 10 Mbps IEEE 802 3 MII 10 Mbps 7 wire interface industry standard IEEE 802 3 full duplex flow control Pro...

Page 325: ...he external transceiver determine the operation speed The transceiver auto negotiates the speed or software controls it via the serial management interface FEC_MDC FEC_MDIO pins to the transceiver Ref...

Page 326: ...ibble of the frame through to the last nibble Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF FEC_RXD0 X X This pin contains the Ethernet input data transferred from the PHY...

Page 327: ...x0000_0000 16 4 4 16 9 0x024 Ethernet Control Register ECR 32 R W 0xF000_0000 16 4 5 16 10 0x040 MII Management Frame Register MMFR 32 R W Undefined 16 4 6 16 10 0x044 MII Speed Control Register MSCR...

Page 328: ...being transmitted This bit is set by one of three conditions 1 A graceful stop initiated by the setting of the TCR GTS bit is now complete 2 A graceful stop initiated by the setting of the TCR TFC_PA...

Page 329: ...the next frame commences This error can only occur in half duplex mode 19 UN Transmit FIFO underrun Indicates the transmit FIFO became empty before the complete frame was transmitted A bad CRC is appe...

Page 330: ...polling until the user sets the bit again signifying additional descriptors are placed into the transmit descriptor ring The TDAR register is cleared at reset when ECR ETHER_EN is cleared or when ECR...

Page 331: ...1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER _EN RESET W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16 6 Ethernet Control Register ECR Table 16 7 EC...

Page 332: ...eld is a don t care Writing this pattern causes the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine During this time contents of th...

Page 333: ...takes effect following a rising or falling edge of FEC_MDC If the internal bus clock is 25 MHz programming this register to 0x0000_0005 results in an FEC_MDC as stated the equation below Eqn 16 1 A t...

Page 334: ...ield Description 31 27 Reserved must be cleared 26 16 MAX_FL Maximum frame length Resets to decimal 1518 Length is measured starting at DA and includes the CRC at the end of the frame Transmit frames...

Page 335: ...0 0 0 0 0 0 0 0 0 0 0 RFC_ PAUSE TFC_ PAUSE FDEN HBC GTS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 16 10 Transmit Control Register TCR Table 16 12 TCR Field Descr...

Page 336: ...and the HB bit in the status register is set if the collision input does not assert within the heartbeat window This bit should only be modified when ECR ETHER_EN is cleared 0 GTS Graceful transmit s...

Page 337: ...dual DA This register is not reset and you must initialize it Offset 0x0E8 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PADDR2 TYPE W...

Page 338: ...criptor Individual Upper Address Register IAUR Table 16 16 IAUR Field Descriptions Field Description 31 0 IADDR1 The upper 32 bits of the 64 bit hash table used in the address recognition process for...

Page 339: ...18 GAUR Field Descriptions Field Description 31 0 GADDR1 The GADDR1 register contains the upper 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a multi...

Page 340: ...riptions Field Description 31 2 Reserved must be cleared 1 0 TFWR Number of bytes written to transmit FIFO before transmission of a frame begins 00 64 bytes written 01 64 bytes written 10 128 bytes wr...

Page 341: ...bit positions This register is undefined at reset and must be initialized prior to operation Table 16 22 FRSR Field Descriptions Field Description 31 11 Reserved must be cleared 10 Reserved must be se...

Page 342: ...tware Ethernet driver interface for transmitting and receiving frames Following the software initialization and operation sections are sections providing a detailed description of the functions of the...

Page 343: ...transmit and receive BDs The buffer descriptors are not initialized by hardware during reset At least one transmit and receive buffer descriptor must be initialized by software before ECR ETHER_EN is...

Page 344: ...the DMA at the same time the E bit is cleared with the default receive buffer length value For end of frame buffers the receive BD is written with L set and information written to the status bits M BC...

Page 345: ...me Written by the FEC 0 The buffer is not the last in a frame 1 The buffer is the last in a frame Offset 0 10 9 Reserved must be cleared Offset 0 8 M Miss Written by the FEC This bit is set by the FEC...

Page 346: ...CR and CL lose their normal meaning and are zero This bit is valid only if the L bit is set Offset 0 0 TR Set if the receive frame is truncated frame length 2047 bytes If the TR bit is set the frame m...

Page 347: ...he next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ETDSR Offset 0 12 TO2 Transmit software ownership This field is reserved...

Page 348: ...ntire data path is reset 16 5 3 User Initialization Prior to Setting ECR ETHER_EN You need to initialize portions the FEC prior to setting the ECR ETHER_EN bit The exact values depend on the particula...

Page 349: ...terface Options The FEC supports an MII interface for 10 100 Mbps Ethernet and a 7 wire serial interface for 10 Mbps Ethernet The RCR MII_MODE bit select the interface mode In MII mode RCR MII_MODE se...

Page 350: ...WR MAC transmit logic asserts FEC_TXEN and starts transmitting the preamble PA sequence the start frame delimiter SFD and then the frame information from the FIFO However the controller defers the tra...

Page 351: ...rted However the entire frame is transmitted no truncation To pause transmission set TCR GTS graceful transmit stop The FEC transmitter stops immediately if transmission is not in progress otherwise i...

Page 352: ...tion has not rejected the frame the receive FIFO signals the frame is accepted and may be passed on to the DMA If the frame is a runt due to collision or is rejected by address recognition the receive...

Page 353: ...etween the DA and the designated PAUSE DA 01 80 C2 00 00 01 If the receive block determines the received frame is a valid PAUSE frame the frame is rejected The receiver detects a PAUSE frame with the...

Page 354: ...tch Pause Frame False False False False True True True True Receive Frame Receive Frame Receive Frame Receive Frame Reject Frame Reject Frame Set BC bit in RCV BD Set MC bit in RCV BD if multicast Set...

Page 355: ...register If the CRC generator selects a bit set in the hash table the frame is accepted otherwise it is rejected For example if eight group addresses are stored in the hash table and random group addr...

Page 356: ...FFF_FFFF 0x2 2 35FF_FFFF_FFFF 0x3 3 B5FF_FFFF_FFFF 0x4 4 95FF_FFFF_FFFF 0x5 5 D5FF_FFFF_FFFF 0x6 6 F5FF_FFFF_FFFF 0x7 7 DBFF_FFFF_FFFF 0x8 8 FBFF_FFFF_FFFF 0x9 9 BBFF_FFFF_FFFF 0xA 10 8BFF_FFFF_FFFF 0...

Page 357: ...39 7FFF_FFFF_FFFF 0x28 40 4FFF_FFFF_FFFF 0x29 41 1FFF_FFFF_FFFF 0x2A 42 3FFF_FFFF_FFFF 0x2B 43 BFFF_FFFF_FFFF 0x2C 44 9FFF_FFFF_FFFF 0x2D 45 DFFF_FFFF_FFFF 0x2E 46 EFFF_FFFF_FFFF 0x2F 47 93FF_FFFF_FFF...

Page 358: ...ment The pause timer uses the transmit backoff timer hardware for tracking the appropriate collision backoff time in half duplex mode The pause timer increments once every slot time until OPD PAUSE_DU...

Page 359: ...ollision occurs within 512 bit times one slot time the retry process is initiated The transmitter waits a random number of slot times If a collision occurs after 512 bit times then no retransmission i...

Page 360: ...elf test feature called heartbeat or signal quality error To signify a good self test the transceiver indicates a collision to the FEC within four microseconds after completion of a frame transmitted...

Page 361: ...hecking cannot be disabled but the CRC error can be ignored if checking is not required 16 5 15 2 4 Frame Length Violation When the receive frame length exceeds MAX_FL bytes the BABR interrupt is gene...

Page 362: ...is capable of operating at higher baud rates up to a maximum of clock 20 with reduced bus loading The maximum communication length and the number of devices that can be connected are limited by a maxi...

Page 363: ...tection Repeated START signal generation detection Acknowledge bit generation detection Bus busy detection General call recognition 10 bit address extension Support System Management Bus Specification...

Page 364: ...bes each user accessible pin signal 17 2 1 SCL Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system 17 2 2 SDA Serial Data Line The bidirectional SDA is the serial data l...

Page 365: ...by their names NOTE A Freescale provided equate or header file is used to translate these names into the appropriate absolute addresses 17 3 2 IIC Address Register 1 IICA1 Address Use Access Base 000...

Page 366: ...e MULT bits is provided below 00 mul 01 01 mul 02 10 mul 04 11 Reserved 5 0 ICR IIC Clock Rate The ICR bits are used to prescale the bus clock for bit rate selection These bits and the MULT bits are u...

Page 367: ...128 Reference Manual Rev 6 17 6 Freescale Semiconductor MULT ICR Hold times s SDA SCL Start SCL Stop 0x2 0x00 3 500 3 000 5 500 0x1 0x07 2 500 4 000 5 250 0x1 0x0B 2 250 4 000 5 250 0x0 0x14 2 125 4 2...

Page 368: ...84 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960...

Page 369: ...ype of transfer required Therefore for address cycles this bit is always high When addressed as a slave this bit should be set by software according to the SRW bit in the status register 0 Receive 1 T...

Page 370: ...GCAEN bit is set and a general call is received 3 If SIICAEN bit is set when the calling address matches the second programmed slave address 4 If ALERTEN bit is set and SMBus alert response address i...

Page 371: ...d this byte is an address byte One byte transfer excluding ACK NCAK bit completes if FACK 1 and this byte is a data byte an ACK or NACK is sent out on the bus by writing 0 or 1 to TXAK after this bit...

Page 372: ...flect every byte that is transmitted on the IIC bus nor can software verify that a byte has been written to the IICD correctly by reading it back In master transmit mode the first byte of data written...

Page 373: ...ons Field Description 7 GCAEN General Call Address Enable The GCAEN bit enables or disables general call address 0 General call address is disabled 1 General call address is enabled 6 ADEXT Address Ex...

Page 374: ...ALERTEN reserved SMBus Alert Response Address Enable The ALERTEN bit enables or disable SMBus alert response address 0 SMBus alert response address matching is disabled 1 SMBus alert response address...

Page 375: ...SMBus This field is used on the device default address or other related address 7 6 5 4 3 2 1 0 R SSLT15 SSLT14 SSLT13 SSLT12 SSLT11 SSLT10 SSLT9 SSLT8 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserve...

Page 376: ...glitches up to width of 3 half IPBUS clock cycles 0100 Filter glitches up to width of 4 half IPBUS clock cycles 0101 Filter glitches up to width of 5 half IPBUS clock cycles 0110 Filter glitches up t...

Page 377: ...ed of four parts START signal Slave address transmission Data transfer STOP signal The STOP signal should not be confused with the CPU STOP instruction The IIC bus system communication is described br...

Page 378: ...ave at the same time However if arbitration is lost during an address cycle the IIC reverts to slave mode and operate correctly even if it is being addressed by another master 17 4 1 3 Data Transfer B...

Page 379: ...t one among the masters The relative priority of the contending masters is determined by a data arbitration procedure a bus master loses arbitration if it transmits logic 1 while another master transm...

Page 380: ...lts the bus clock and forces the master clock into wait states until the slave releases the SCL line 17 4 1 9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down th...

Page 381: ...ding acknowledge bit A2 the procedure is the same as that described for a master transmitter addressing a slave receiver After the repeated START condition Sr a matching slave remembers that it was ad...

Page 382: ...s status 17 4 4 1 Timeouts The TTIMEOUT MIN parameter allows a master or slave to conclude that a defective device is holding the clock low indefinitely or a master is intentionally trying to drive de...

Page 383: ...XT When master mode the I2C must not cumulatively extend its clock cycles for a period greater than TLOW MEXT within a byte where each byte is defined as START to ACK ACK to ACK or ACK to STOP When CS...

Page 384: ...ince such a condition may occur on the last byte of the transfer it is required that SMBus devices have the ability to generate the not acknowledge after the transfer of each byte and before the compl...

Page 385: ...a arbitration process and the ARBL bit in the status register is set Arbitration is lost in the following circumstances SDA sampled as a low when the master drives a high during an address or data tra...

Page 386: ...ck and data lines for I2C module The width of the glitch to absorb can be specified in terms of number of half bus clock cycles A single glitch filter control register is provided as IICFLT Effectivel...

Page 387: ...nable TX 6 Write IICC1 to enable MST master mode 7 Write IICD with the address of the target slave The LSB of this byte determines whether the communication is master receive or transmit Module Use Th...

Page 388: ...CN128 Reference Manual Rev 6 Freescale Semiconductor 17 27 IICSLTH IIC SCL Low Time Out Register High IICSLTL SSLT 7 0 IIC SCL Low Time Out Register Low SSLT 15 8 IICFLT FLT3 FLT2 FLT1 FLT0 0 0 0 0 II...

Page 389: ...ext Byte Read Data from IICD and Store Switch to Rx Mode Dummy Read from IICD RTI Y N Y Y Y Y Y Y Y Y Y N N N N N N N N N Y TX RX RX TX Write Read N IICIF Address Transfer Data Transfer MST 0 MST 0 Se...

Page 390: ...yte Read Data from IICD and Store Switch to Rx Mode Dummy Read from IICD RTI Y N Y Y Y Y Y Y Y Y Y N N N N N N N N N Y TX RX RX TX Write Read N Address Transfer MST 0 MST 0 See Note 1 Y N FACK Flow Ch...

Page 391: ...e MTIMs are collectively called MTIMx For example MTIMx for an MCU with two MTIMs refers to MTIM1 and MTIM2 For MCUs that have exactly one MTIM it is always referred to as MTIM1 Use pin mux control re...

Page 392: ...e the MTIM can be used to bring the MCU out of wait mode if the timer overflow interrupt is enabled For lowest possible current consumption the MTIM must be stopped by software if not needed as an int...

Page 393: ...Block Diagram 18 2 External Signal Description The MTIM includes one external signal TCLK used to input an external clock when selected as the MTIM clock source The signal properties of TCLK are show...

Page 394: ...bit status and control register An 8 bit clock configuration register An 8 bit counter register An 8 bit modulo register Refer to the direct page register summary in Chapter 4 Memory for the absolute...

Page 395: ...counter has not reached the overflow value in the MTIM modulo register 1 MTIM counter has reached the overflow value in the MTIM modulo register 6 TOIE MTIM Overflow Interrupt Enable This read write...

Page 396: ...000 00 Encoding 0 Bus clock BUSCLK 01 Encoding 1 Fixed frequency clock XCLK 10 Encoding 3 External source TCLK pin falling edge 11 Encoding 4 External source TCLK pin rising edge All other encodings...

Page 397: ...Description 7 0 COUNT MTIM Count These eight read only bits contain the current value of the 8 bit counter Writes have no effect to this register Reset clears the count to 0x00 7 6 5 4 3 2 1 0 R MOD W...

Page 398: ...ale values are software selectable clock source divided by 1 2 4 8 16 32 64 128 or 256 The prescaler select bits PS 3 0 in MTIMSC select the desired prescale value If the counter is active TSTP 0 when...

Page 399: ...clock source could be any of the five possible choices The prescaler is set to PS 0010 or divide by 4 The modulo value in the MTIMMOD register is set to 0xAA When the counter MTIMCNT reaches the modul...

Page 400: ...g functions are based on a 16 bit counter with prescaler and modulo features to control frequency and range period between overflows of the time reference This timing system is ideally suited for a wi...

Page 401: ...annels to switch to center aligned PWM mode When center aligned PWM mode is selected input capture output compare and edge aligned PWM functions are not available on any channels of this TPM module Wh...

Page 402: ...called center aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero This type of PWM is required for types of motors used in small appli...

Page 403: ...A counter reset CLKSB CLKSA 1 2 4 8 16 32 64 or 128 bus clock external clock synchronizer 16 bit comparator 16 bit latch channel 1 ELS1B ELS1A CH1IE CH1F TPM counter Port logic Interrupt logic MS1B MS...

Page 404: ...refore allowing its use as a timer ELSnB ELSnA 0 0 For proper TPM operation the external clock frequency must not exceed one fourth of the bus clock frequency 19 2 1 2 TPMxCHn TPM Channel n I O Pins T...

Page 405: ...When ELSnB is set and ELSnA is cleared the TPMxCHn pin is forced high at the start of each new period TPMxCNT 0x0000 and it is forced low when the channel value register matches the TPM counter When E...

Page 406: ...ches the TPM counter and it is cleared when the TPM counter is counting down and the channel value register matches the TPM counter Figure 19 4 High True Pulse of a Center Aligned PWM Figure 19 5 Low...

Page 407: ...rflow interrupt enable This read write bit enables TPM overflow interrupts If TOIE is set an interrupt is generated when TOF equals one Reset clears TOIE 0 TOF interrupts inhibited use for software po...

Page 408: ...e to the timer status control register TPMxSC Reset clears the TPM counter registers Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter TPMxCNTH TPMxCNTL and resets the coherency me...

Page 409: ...registers to 0x0000 that results in a free running timer counter modulo disabled Writes to any of the registers TPMxMODH and TPMxMODL actually writes to buffer registers and the registers are updated...

Page 410: ...ompleted CHnF remains set This is done so a CHnF interrupt request is not lost due to clearing a previous CHnF Reset clears this bit Writing a logic 1 to CHnF has no effect 0 No input capture or outpu...

Page 411: ...vel Selection CPWMS MSnB MSnA ELSnB ELSnA Mode Configuration X XX 00 Pin is not controlled by TPM It is reverted to general purpose I O or other peripheral control 0 00 01 Input capture Capture on ris...

Page 412: ...This latching mechanism allows coherent 16 bit writes in either big endian or little endian order that is friendly to various compiler implementations When BDM is active the coherency mechanism is fr...

Page 413: ...properly aligned to bus clock transitions Therefore in order to meet Nyquist criteria considering also jitter the frequency of the external clock source must not exceed 1 4 of the bus clock frequency...

Page 414: ...asic mode of operation for the corresponding channel Choices include input capture output compare and edge aligned PWM 19 4 2 1 Input Capture Mode With the input capture function the TPM can capture t...

Page 415: ...ignal is determined by ELSnA bit 0 and 100 duty cycle cases are possible The time between the modulus overflow and the channel match value TPMxCnVH TPMxCnVL is the pulse width or duty cycle Figure 19...

Page 416: ...imitation The resulting period is much longer than required for normal applications All zeros in TPMxMODH TPMxMODL is a special case that must not be used with center aligned PWM mode When CPWMS is cl...

Page 417: ...er is a free running counter the update is made when the TPM counter changes from 0xFFFE to 0xFFFF When TPMxCNTH TPMxCNTL equals TPMxMODH TPMxMODL the TPM can optionally generate a TOF interrupt at th...

Page 418: ...e new event 19 6 2 1 Timer Overflow Interrupt TOF Description The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system general pur...

Page 419: ...h time the main timer counter matches the 16 bit value in the channel value register The flag is cleared by the two step sequence described in Section 19 6 2 Description of Interrupt Operation 19 6 2...

Page 420: ...kage pin BKGD An on chip trace buffer allows a stream of compressed processor execution status packets to be recorded for subsequent retrieval to provide program and partial data trace capabilities Th...

Page 421: ...be halted which many real time embedded applications cannot support The core includes a variety of internal breakpoint registers which can be configured to trigger and generate a special interrupt Th...

Page 422: ...re of compressed processor status and debug data into on chip trace buffer provides program and optional slave bus data trace capabilities On chip trace buffer provides programmable start stop recordi...

Page 423: ...of ways The BKGD pin is low during POR The BKGD pin is low immediately after a BDM initiated force reset see CSR2 BDFR in Section 20 3 3 Configuration Status Register 2 CSR2 for details A background d...

Page 424: ...ignal Descriptions Table 20 3 describes the debug module s 1 pin external signal BKGD A standard 6 pin debug connector is shown in Section 20 4 4 Freescale Recommended BDM Pinout Table 20 3 Debug Modu...

Page 425: ...less of the number of implemented bits and unimplemented bits are reserved and must be cleared These registers are also accessed through the BDM port by the commands WRITE_DREG and READ_DREG described...

Page 426: ...ough the supervisor programming model using the WDEBUG instruction 20 3 1 Configuration Status Register CSR CSR defines the debug configuration for the processor and memory subsystem and contains stat...

Page 427: ...breakpoint 0110 Level 2 breakpoint triggered 27 FOF Fault on fault Indicates a catastrophic halt occurred and forced entry into BDM FOF is cleared by reset or when CSR is read from the BDM port only...

Page 428: ...abilities 00 No operand data is displayed 01 Capture all write data 10 Capture all read data 11 Capture all read and write data 10 UHE User halt enable Selects the CPU privilege level required to exec...

Page 429: ...ted On receipt of the GO command the processor executes the next instruction and halts again This process continues until SSM is cleared 3 2 Reserved must be cleared 1 FID Force ipg_debug The core gen...

Page 430: ...PC ENB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 4 Extended Configuration Status Register XCSR Table 20 7 XCSR Field Descriptions Field Description 31 CPUHALT Indicates that the CPU is in the...

Page 431: ...onous BDC clock typically 10 MHz 1 Synchronous bus clock CPU clock divided by 2 The initial state of the XCSR CLKSW bit is loaded by the hardware in response to certain reset events and the state of t...

Page 432: ...ace synchronization and code profiling As described in XCSR APCSC when the enabled periodic timer expires a SYNC_PC command is sent to the ColdFire CPU which generates a forced instruction fetch of th...

Page 433: ...power on reset and is unaffected by any other reset 0 After a computer operating properly reset the device immediately enters normal operation mode 1 A computer operating properly reset immediately h...

Page 434: ...sion level of the 1 pin debug module implemented in the ColdFire core For this device this field is 0x1 15 8 PSTBWA PST trace buffer write address Indicates the current write address of the PST trace...

Page 435: ...d non obtrusive are defined as Non obtrusive The core is not halted The PST trace buffer is overwritten unless a PSTB start stop combination results in less than or equal to 64 PSTB captures Obtrusive...

Page 436: ...k divide by 8 0 Input to the flash clock divider is the bus clock 1 Input to the flash clock divider is the bus clock divided by 8 29 24 BFCDIV BDM flash clock divider The BFCDIV8 and BFCDIV fields sp...

Page 437: ...te only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R SZ TT TM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 438: ...s the R bit in address comparisons 14 13 SZM Size mask Masks the corresponding SZ bit in address comparisons 12 11 TTM Transfer type mask Masks the corresponding TT bit in address comparisons 10 8 TMM...

Page 439: ...0 TRC Trigger response control Determines how the processor responds to a completed trigger condition The trigger response is displayed on PST 00 Display on PST only 01 Processor halt 10 Debug interru...

Page 440: ...a Data_condition is optional The ColdFire debug architecture supports the creation of single or double level triggers 0 Level 2 trigger PC_condition Address_range Data_condition 1 Level 2 trigger PC_c...

Page 441: ...data value other than the DBR contents 0 No inversion 1 Invert data breakpoint comparators 4 2 L1EA Enable level 1 address breakpoint Setting an L1EA bit enables the corresponding address breakpoint...

Page 442: ...isor write only BDM write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Address Reset Figure 20 10 Program Counter Breakpoint Register 0 PBR0 Table 20...

Page 443: ...tions NOTE Version 1 ColdFire core devices implement a 24 bit 16 MB address map When programming these registers with a 32 bit address the upper byte must be zero filled DRc 0x09 PBMR Access Superviso...

Page 444: ...pecific addresses are programmed into ABLR Table 20 19 ABHR Field Description Field Description 31 0 Address High address Holds the 32 bit address marking the upper bound of the address breakpoint ran...

Page 445: ...function of ABHR ABLR and AATR Data_breakpoint is a function of DBR and DBMR In all cases the data breakpoints can be included with an address breakpoint to further qualify a trigger event as an optio...

Page 446: ...akpoints and single instruction step Features of the background debug controller BDC include Single dedicated pin for mode selection and background communications Special BDC registers not located in...

Page 447: ...ARD IRD bits Table 20 23 CPU Halt Sources Halt Source Halt Timing Description Fault on fault Immediate Refers to the occurrence of any fault while exception processing For example a bus error is signa...

Page 448: ...g the next sequential instruction the instruction following STOP PSTB full condition Pending PSTB PSTB obtrusive recording mode pends halt in the processor if the trace buffer reaches its full thresho...

Page 449: ...tive background halt mode rather than normal operating mode and then release BKGD It is not necessary to reset the target MCU to communicate with it through the background debug interface There is als...

Page 450: ...locks in the target BDC but asynchronous to the external host The internal BDC clock signal is shown for reference in counting cycles Figure 20 16 shows an external host transmitting a logic 1 or 0 to...

Page 451: ...here is a 0 1 cycle delay from the host generated falling edge on BKGD to the start of the bit time as perceived by the target MCU The host initiates the bit time but the target MCU finishes it Becaus...

Page 452: ...et is based on transmission of one or more 8 bit data packets per operation Each operation begins with a host to target transmission of an 8 bit command code packet The command code definition broadly...

Page 453: ...0 0 R W 1 SZ MCMD W if addr R W if data Command Extension Bytes Address Data Core Register Commands 7 6 5 4 3 2 1 0 W CRG R W CRN R W Command Extension Bytes Data PST Trace Buffer Read Commands 7 6 5...

Page 454: ...te 1111 Read write of the debug CSR3 most significant byte 3 2 SZ Memory operand size Defines the size of the memory reference 00 8 bit byte 01 16 bit word 10 32 bit long 1 0 MCMD Memory command Defin...

Page 455: ...to target direction wd sz write data size defined by sz in the host to target direction ss the contents of XCSR 31 24 in the target to host direction STATUS sz memory operand size 0b00 byte 0b01 word...

Page 456: ...e sequential operands GO Non Intrusive Yes 0x08 d Resume the CPU s execution3 NOP Non Intrusive Yes 0x00 d No operation READ_CREG Active Background Yes 0xE0 CRN d rd32 Read one of the CPU s control re...

Page 457: ...one of the CPU s control registers WRITE_DREG Non Intrusive Yes 0x80 CRN wd32 d Write one of the debug module s control registers WRITE_MEM sz Non Intrusive Yes 0x10 4 x sz ad24 wd sz d Write the appr...

Page 458: ...followed by an ACK pulse 20 4 1 5 3 ACK_ENABLE Enables the hardware handshake protocol in the serial communication The hardware handshake is implemented by an acknowledge ACK pulse issued by the targ...

Page 459: ...ng to send the BACKGROUND command the first time Normally the development host would set ENBDM once at the beginning of a debug session or after a target system reset and then leave the ENBDM bit set...

Page 460: ...is returned before the read data XCSR_SB reflects the state after the memory read was performed NOTE DUMP_MEM _WS does not check for a valid address it is a valid command only when preceded by NOP RE...

Page 461: ...and store the updated address in the temporary register If the with status option is specified FILL_MEM sz Write memory specified by debug address register then increment address Non intrusive 0x12 M...

Page 462: ...size to be dynamically altered The examples show the FILL_MEM B _WS FILL_MEM W _WS and FILL_MEM L _WS commands 20 4 1 5 7 GO This command is used to exit active background halt mode and begin or resu...

Page 463: ...an illegal operation and no operation is performed 20 4 1 5 10 READ_DREG This command reads the selected debug control register and returns the 32 bit result This register grouping includes the CSR XC...

Page 464: ...ad memory at the specified address Non intrusive 0x30 Address 23 0 Memory data 7 0 host target host target D L Y target host 0x34 Address 23 0 Memory data 15 8 Memory data 7 0 host target host target...

Page 465: ...An Dn and returns the 32 bit result See Table 20 24 for the CRN details when CRG is 01 If the processor is not halted this command is rejected as an illegal operation and no operation is performed 20...

Page 466: ...cleared then a 2 byte address is captured else a 3 byte address is captured The specific sequence of PST and DDATA values is defined as 1 Debug signals a SYNC_PC command is pending 2 CPU completes th...

Page 467: ...performed 20 4 1 5 19 WRITE_DREG This command writes the 32 bit operand to the selected debug control register This grouping includes all the debug control registers X CSRn BAAR AATR TDR PBRn PBMR AB...

Page 468: ...d WRITE_MEM L _WS commands WRITE_MEM sz Write memory at the specified address Non intrusive 0x10 Address 23 0 Memory data 7 0 host target host target host target D L Y 0x14 Address 23 0 Memory data 15...

Page 469: ...xecuted in any mode 20 4 1 5 23 WRITE_CSR2_BYTE Write the most significant byte of CSR2 CSR2 31 24 This command can be executed in any mode 20 4 1 5 24 WRITE_CSR3_BYTE Write the most significant byte...

Page 470: ...D GO NOP SYNC_PC The ACK pulse is not issued earlier than 32 BDC clock cycles after the BDC command was issued The end of the BDC command is assumed to be the 16th BDC clock cycle of the last bit This...

Page 471: ...ere the host initiates the transmission by issuing a negative edge in the BKGD pin the serial interface ACK handshake pulse is initiated by the target MCU The hardware handshake protocol in Figure 20...

Page 472: ...quires CPU execution This prevents the new command from being discarded at the debug CPU interface due to the pending command being executed by the CPU Any new command should be issued only after XCSR...

Page 473: ...pulse and the sync request pulse This conflict could occur if a pod device is connected to the target BKGD pin and the target is already executing a BDC command Consider that the target CPU is executi...

Page 474: ...at have the status register included in the retrieved bit stream do not perform the hardware handshake protocol Therefore the target does not respond with an ACK pulse for those commands even if the h...

Page 475: ...or accesses mapped to the slave peripheral bus Displayed information includes PST marker plus captured operand value as DDATA Captured operand creates the appropriate number of DDATA entries each with...

Page 476: ...dress may be displayed on DDATA depending on the CSR settings CSR also controls the number of address bytes displayed indicated by the PST marker value preceding the DDATA nibble that begins the data...

Page 477: ...aded is configurable 2 or 3 bytes where the encoding is 0x0D and 0x0E respectively 0x1B This value signals there has been a change in the breakpoint trigger state machine It appears as a single marker...

Page 478: ...d loaded in the trace buffer each entry is six bits in size therefore the type of the entry can easily be determined when post processing the PSTB See Figure 20 25 Figure 20 25 V1 PST DDATA Trace Buff...

Page 479: ...0b4 4e73 rte exit This ISR executes mostly as straight line code there is a single conditional branch PC 0x10A6 which is taken in this example The following description includes the PST and DDATA valu...

Page 480: ...and where the definition is optional operand information defined by the setting of the CSR and indicates the presence of one value from the list The CSR provides capabilities to display operands based...

Page 481: ...PST 0x05 bset b l data ea x PST 0x01 PST 0x08 DD source PST 0x08 DD destination bset b l Dy ea x PST 0x01 PST 0x08 DD source PST 0x08 DD destination bsr b w l PST 0x05 PST 0x0B DD destination operand...

Page 482: ...tion move w ea y ea x PST 0x01 PST 0x09 DD source PST 0x09 DD destination move w CCR Dx PST 0x01 move w Dy data CCR PST 0x01 movea l ea y Ax PST 0x01 PST 0x0B DD source movea w ea y Ax PST 0x01 PST 0x...

Page 483: ...ion suba l ea y Ax PST 0x01 PST 0x0B DD source operand subi l data Dx PST 0x01 subq l data ea x PST 0x01 PST 0x0B DD source PST 0x0B DD destination subx l Dy Dx PST 0x01 swap w Dx PST 0x01 tas b ea x...

Page 484: ...uence is equivalent to normal exception processing The PST DDATA specification for the reset exception is shown below Exception Processing PST 0x1C 0x1C PST 0x05 PST 0x0 DE DD target initial PC The in...

Page 485: ...ndard RS 232 serial port a parallel printer port or some other type of communications such as a universal serial bus USB to communicate between the host PC and the pod The pod typically connects to th...

Page 486: ...t Controller FEC Timer PWM Module TPM and Modulo Timer MTIM In chapter introduction sections added GPIO note Use pin mux control registers from Section 2 3 Pin Mux Controls to assign GPIO signals to t...

Page 487: ...d a note in introduction section to ignore references to stop1 Serial Communication Interface SCI Changed bus clock to SCI module clock Timer PWM Module TPM Updated the description of fixed frequency...

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