Inter-Integrated Circuit (IIC)
MCF51CN128 Reference Manual, Rev. 6
17-20
Freescale Semiconductor
17.4.2
10-bit Address
For 10-bit addressing, 11110b is used for the first 5 bits of the first address byte. Various combinations of
read/write formats are possible within a transfer that includes 10-bit addressing.
17.4.2.1
Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed (see
). When a 10-bit address follows a START
condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with
its own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one
device finds a match and generates an acknowledge (A1). Each slave that finds a match compares the eight
bits of the second byte of the slave address with its own address, but only one slave finds a match and
generate an acknowledge (A2). The matching slave remains addressed by the master until it receives a
STOP condition (P) or a repeated START condition (Sr) followed by a different slave address.
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
17.4.2.2
Master-Receiver Addresses a Slave-Transmitter
The transfer direction is changed after the second R/W bit (see
). Up to and including
acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a
slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed
before. This slave then checks whether the first seven bits of the first byte of the slave address following
Sr are the same as they were after the START condition (S), and tests whether the eighth (R/W) bit is 1. If
there is a match, the slave considers that it is addressed as a transmitter and generates acknowledge A3.
The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START
condition (Sr) followed by a different slave address.
After a repeated START condition (Sr), all other slave devices also compare the first seven bits of the first
byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them
are addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit devices) does
not match.
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
S
Slave Address 1st 7 bits
R/W
A1
Slave Address 2nd byte
A2
Data
A
...
Data
A/A
P
11110 + AD10 + AD9
0
AD[8:1]
Table 17-11. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address
S
Slave Address
1st 7 bits
R/W
A1
Slave Address
2nd byte
A2
Sr
Slave Address
1st 7 bits
R/W
A3
Data
A
...
Data
A
P
11110 + AD10 + AD9
0
AD[8:1]
11110 + AD10 + AD9
1
Table 17-12. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
