Mini-FlexBus
11-9
Freescale Semiconductor
MCF51CN128 Reference Manual, Rev. 6
11.4.4
Address/Data Bus Multiplexing
The interface supports a single
-bit wide multiplexed address and data bus (FB_AD[
:0]). The full
-bit address is always driven on the first clock of a bus cycle. During the data phase, the FB_AD[
:0]
lines used for data are determined by the programmed port size for the corresponding chip select. The
device continues to drive the address on any FB_AD[
:0] lines not used for data.
The table below lists the supported combinations of address and data bus widths.
11.4.5
Bus Cycle Execution
, basic bus operations occur in four clocks:
1. S0: At the first clock edge, the address, attributes, and FB_ALE are driven.
2. S1: FB_CS
n
is asserted at the second rising clock edge to indicate the device selected; by that time,
the address and attributes are valid and stable. FB_ALE is negated at this edge.
For a write transfer, data is driven on the bus at this clock edge and continues to be driven until one
clock cycle after FB_CS
n
negates. For a read transfer, data is also driven into the device during this
cycle.
3. S2: Read data is sampled on the third clock edge. After this edge read data can be tri-stated.
4. S3: FB_CS
n
is negated at the fourth rising clock edge. This last clock of the bus cycle uses what
would be an idle clock between cycles to provide hold time for address, attributes, and write data.
Table 11-8. Mini-FlexBus Multiplexed Operating Modes
Port Size & Phase
FB_AD
[19:16]
[15:8]
[7:0]
16
-bit
Address phase
Address
Data phase
Address
Data
8-bit
Address phase
Address
Data phase
Address
Data
20
19
20
15
15
