Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual
,
Rev. 6
20-18
Freescale Semiconductor
development system. BAAR is loaded any time AATR is written and is initialized to a value of 0x05,
setting supervisor data as the default address space. The upper 24 bits of this register are reserved for future
use and any attempted write of these bits is ignored.
20.3.6
Address Attribute Trigger Register (AATR)
AATR defines address attributes and a mask to be matched in the trigger. The register value is compared
with address attribute signals from the processor’s high-speed local bus, as defined by the setting of the
trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06
using the WDEBUG instruction and through the BDM port using the WRITE_DREG command.
DRc: 0x05 (BAAR)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 R
SZ
TT
TM
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Figure 20-7. BDM Address Attribute Register (BAAR)
Table 20-12. BAAR Field Descriptions
Field
Description
31–8
Reserved for future use by the debug module, must be cleared.
7
R
Read/Write.
0 Write
1 Read
6–5
SZ
Size.
00 Longword
01 Byte
10 Word
11 Reserved
4–3
TT
Transfer type. See the TT definition in the AATR description,
Section 20.3.6, “Address Attribute Trigger Register
2–0
TM
Transfer modifier. See the TM definition in the AATR description,
Section 20.3.6, “Address Attribute Trigger Register
DRc: 0x06 (AATR)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM SZM
TTM
TMM
R
SZ
TT
TM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Figure 20-8. Address Attribute Trigger Register (AATR)
